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* Remove old hack for compiling with gcc-4.0.Bob Wilson2011-09-261-25/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140573 91177308-0d34-0410-b5e6-96231b3b80d8
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target hook for pseudo instruction expansion.Jakob Stoklund Olesen2011-09-251-0/+1
| | | | | | | | | | | | Many targets use pseudo instructions to help register allocation. Like the COPY instruction, these pseudos can be expanded after register allocation. The early expansion can make life easier for PEI and the post-ra scheduler. This patch adds a hook that is called for all remaining pseudo instructions from the ExpandPostRAPseudos pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-234-6/+19
| | | | | | Fixes part of PR10700. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore hasPostISelHook tblgen flag.Andrew Trick2011-09-203-1/+4
| | | | | | | | | | | No functionality change. The hook makes it explicit which patterns require "special" handling. i.e. it self-documents tblgen deficiencies. I plan to add verification in ExpandISelPseudos and Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's too fragile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-203-4/+1
| | | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more of llvmc and dependencies.Eric Christopher2011-09-204-3176/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140121 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
* Better Error ReportingDavid Greene2011-09-191-0/+4
| | | | | | | Report missing template arguments more helpfully by supplying the name of the missing argument in the error message. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140034 91177308-0d34-0410-b5e6-96231b3b80d8
* Migrate this to use clang by default as well.Eric Christopher2011-09-161-6/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139936 91177308-0d34-0410-b5e6-96231b3b80d8
* We now look for clang, then llvm-gcc, then gcc as our compiler. We don't needEric Christopher2011-09-161-12/+0
| | | | | | this anymore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139935 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND ↵Craig Topper2011-09-141-5/+0
| | | | | | from being recognized by disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
* [tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to ↵Argyrios Kyrtzidis2011-09-131-2/+7
| | | | | | attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139617 91177308-0d34-0410-b5e6-96231b3b80d8
* In ClangAttrEmitter.cpp emit code that allows attributes to keep their ↵Argyrios Kyrtzidis2011-09-131-3/+3
| | | | | | source range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139598 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper2011-09-131-3/+1
| | | | | | being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-1/+1
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP ↵Craig Topper2011-09-112-3/+6
| | | | | | disassembling to ignore OpSize and REX.W. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
* Update Clang AST attribute reader tblgen generation to match with ASTReader ↵Douglas Gregor2011-09-091-1/+1
| | | | | | change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139414 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to handle the case where emitPredicateMatch returns false. ↵Eli Friedman2011-09-081-1/+2
| | | | | | Noticed by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139317 91177308-0d34-0410-b5e6-96231b3b80d8
* Added LateParsed property to TableGen attributes.Caitlin Sadowski2011-09-083-0/+43
| | | | | | This patch was written by DeLesley Hutchins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139300 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix warning on windows; use of comparison with bool argument.James Molloy2011-09-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139286 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a use of freed string contents.Andrew Trick2011-09-081-4/+4
| | | | | | | Speculatively try to fix our windows testers with a patch I found on the internet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139279 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2011-09-081-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139278 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRBT.Jim Grosbach2011-09-071-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 parsing and encoding for LDR(immediate).Jim Grosbach2011-09-071-0/+1
| | | | | | | | | | The immediate offset of the non-writeback i8 form (encoding T4) allows negative offsets only. The positive offset form of the encoding is the LDRT instruction. Immediate offsets in the range [0,255] use encoding T3 instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy2011-09-073-6/+58
| | | | | | predicate checking to the Disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
* Dependency should be on the output file name, not the dependency fileJoerg Sonnenberger2011-09-071-1/+1
| | | | | | | name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139220 91177308-0d34-0410-b5e6-96231b3b80d8
* valgrind: Suppress glibc's optiized strcasecmp harder.Benjamin Kramer2011-09-031-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139084 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to silence known valgrind errors.Andrew Trick2011-09-021-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139048 91177308-0d34-0410-b5e6-96231b3b80d8
* Make RecordVal Name an InitDavid Greene2011-09-022-3/+16
| | | | | | | | | Store a RecordVal's name as an Init to allow class-qualified Record members to reference Records that have Init names. We'll use this to provide more programmability in how we name defs and their associated members. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139031 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.Kevin Enderby2011-09-021-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
* Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form ↵Craig Topper2011-09-021-26/+23
| | | | | | from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up r137380 based on post-commit review by Jim Grosbach.James Molloy2011-09-011-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
* lit: Normalize pathsep slashes also on %T.NAKAMURA Takumi2011-08-311-0/+1
| | | | | | On Python-w32 with mingw msys bash, %T was replaced to "x:\foo\bar...". msys bash cannot handle DOSish paths. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138852 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow up to r138791.Evan Cheng2011-08-303-0/+3
| | | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
* Lit option for ignoring stderr output.Andrew Trick2011-08-304-4/+11
| | | | | | | | | This is useful for testing a build a temporarily hand instrumented build. Patch by arrowdodger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138804 91177308-0d34-0410-b5e6-96231b3b80d8
* Add vvvv support to disassembling of instructions with MRMDestMem and ↵Craig Topper2011-08-301-4/+27
| | | | | | MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217Kevin Enderby2011-08-291-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverted r138652, valgrind doesn't understand obj:*/tblgen.Andrew Trick2011-08-272-12/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138703 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-0/+1
| | | | | | decoding bug this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
* valgrind: Always suppress tblgen leaks.Andrew Trick2011-08-262-0/+12
| | | | | | | I'll clean up the rest of the XFAIL: vg_leak lines if this works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138652 91177308-0d34-0410-b5e6-96231b3b80d8
* lit: Add %T as a replacement for the output directoryDouglas Gregor2011-08-261-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138640 91177308-0d34-0410-b5e6-96231b3b80d8
* Give ATTR_VEX higher priority when generating the disassembler context ↵Craig Topper2011-08-251-2/+2
| | | | | | table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb parsing and encoding support for ADD SP instructions.Jim Grosbach2011-08-241-1/+2
| | | | | | | | Fix the test FIXME and add parsing support for the ADD (SP plus immediate) and ADD (SP plus register) instruction forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-0/+1
| | | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
* Thread safety: Adding in an option for variadic expr* array of argumentsCaitlin Sadowski2011-08-231-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138351 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix fpimmm->fpimm typo.Eric Christopher2011-08-231-1/+1
| | | | | | | Patch by Micah Villmow! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138330 91177308-0d34-0410-b5e6-96231b3b80d8
* utils/lit/lit/TestingConfig.py: Pass TEMP and TMP to tests on Win32 hosts.NAKAMURA Takumi2011-08-201-0/+2
| | | | | | Win32 GetTempPath() tends to pick up %WINDIR% when neither TEMP nor TMP was found. %WINDIR% should not be treated writable on recent Windows OS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138192 91177308-0d34-0410-b5e6-96231b3b80d8
* utils/lit/lit/TestingConfig.py: Split out environment vars for Win32.NAKAMURA Takumi2011-08-201-3/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138191 91177308-0d34-0410-b5e6-96231b3b80d8
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