From 05d0265fef651de152c8127aa701e689555649f3 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 18 Apr 2011 23:59:50 +0000 Subject: docs: Use as Heading elements instead of
. H1 ... doc_title H2 ... doc_section H3 ... doc_subsection H4 ... doc_subsubsection git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129736 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/WritingAnLLVMBackend.html | 112 ++++++++++++++++++++--------------------- 1 file changed, 56 insertions(+), 56 deletions(-) (limited to 'docs/WritingAnLLVMBackend.html') diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html index 4798cdf..c8dcb8a 100644 --- a/docs/WritingAnLLVMBackend.html +++ b/docs/WritingAnLLVMBackend.html @@ -9,9 +9,9 @@ -
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Writing an LLVM Compiler Backend -

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  1. Introduction @@ -61,9 +61,9 @@
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Introduction -

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@@ -93,9 +93,9 @@ conventions.
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Audience -

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@@ -106,9 +106,9 @@ generate code for a specific hardware or software target.
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Prerequisite Reading -

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@@ -155,9 +155,9 @@ machine dependent features.
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Basic Steps -

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@@ -220,9 +220,9 @@ that the class will need and which components will need to be subclassed.
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Preliminaries -

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@@ -282,9 +282,9 @@ regenerate configure by running ./autoconf/AutoRegen.sh.
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Target Machine -

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@@ -424,9 +424,9 @@ SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &a
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Target Registration -

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@@ -480,9 +480,9 @@ For more information, see
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Register Set and Register Classes -

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@@ -517,9 +517,9 @@ implementation of XXXRegisterInfo requires hand-coding.
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Defining a Register -

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@@ -700,9 +700,9 @@ fields of a register's TargetRegisterDesc.
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Defining a Register Class -

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@@ -894,10 +894,10 @@ namespace SP { // Register class instances
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Implement a subclass of TargetRegisterInfo -

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@@ -934,9 +934,9 @@ implementation in SparcRegisterInfo.cpp:
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Instruction Set -

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@@ -1191,9 +1191,9 @@ correspond to the values in SparcInstrInfo.td. I.e.,
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Instruction Operand Mapping -

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@@ -1283,10 +1283,10 @@ the rd, rs1, and rs2 fields respectively.
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Implement a subclass of TargetInstrInfo -

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@@ -1327,9 +1327,9 @@ implementation in SparcInstrInfo.cpp:
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Branch Folding and If Conversion -

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@@ -1486,9 +1486,9 @@ branch.

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Instruction Selector -

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@@ -1645,9 +1645,9 @@ SDNode *Select_ISD_STORE(const SDValue &N) {
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The SelectionDAG Legalize Phase -

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@@ -1719,9 +1719,9 @@ contains examples of all four LegalAction values.
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Promote -

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@@ -1742,9 +1742,9 @@ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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Expand -

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@@ -1767,9 +1767,9 @@ setOperationAction(ISD::FCOS, MVT::f32, Expand);
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Custom -

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@@ -1833,9 +1833,9 @@ static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
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Legal -

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@@ -1866,9 +1866,9 @@ if (TM.getSubtarget<SparcSubtarget>().isV9())
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Calling Conventions -

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@@ -2016,9 +2016,9 @@ def RetCC_X86_32 : CallingConv<[
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Assembly Printer -

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@@ -2171,9 +2171,9 @@ output.
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Subtarget Support -

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@@ -2289,9 +2289,9 @@ XXXSubtarget::XXXSubtarget(const Module &M, const std::string &FS) {
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JIT Support -

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@@ -2336,9 +2336,9 @@ that write data (in bytes, words, strings, etc.) to the output stream.
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Machine Code Emitter -

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@@ -2478,9 +2478,9 @@ enum RelocationType {
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Target JIT Info -

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