From 3f63a589788995a724bc4587d022fe15ea8576ba Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 30 Jul 2012 18:34:14 +0000 Subject: Add MachineInstr::isTransient(). This is a cleaned up version of the isFree() function in MachineTraceMetrics.cpp. Transient instructions are very unlikely to produce any code in the final output. Either because they get eliminated by RegisterCoalescing, or because they are pseudo-instructions like labels and debug values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160977 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include/llvm/CodeGen/MachineInstr.h') diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 65093d7..30433a2 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -635,6 +635,30 @@ public: getOperand(0).getSubReg() == getOperand(1).getSubReg(); } + /// isTransient - Return true if this is a transient instruction that is + /// either very likely to be eliminated during register allocation (such as + /// copy-like instructions), or if this instruction doesn't have an + /// execution-time cost. + bool isTransient() const { + switch(getOpcode()) { + default: return false; + // Copy-like instructions are usually eliminated during register allocation. + case TargetOpcode::PHI: + case TargetOpcode::COPY: + case TargetOpcode::INSERT_SUBREG: + case TargetOpcode::SUBREG_TO_REG: + case TargetOpcode::REG_SEQUENCE: + // Pseudo-instructions that don't produce any real output. + case TargetOpcode::IMPLICIT_DEF: + case TargetOpcode::KILL: + case TargetOpcode::PROLOG_LABEL: + case TargetOpcode::EH_LABEL: + case TargetOpcode::GC_LABEL: + case TargetOpcode::DBG_VALUE: + return true; + } + } + /// getBundleSize - Return the number of instructions inside the MI bundle. unsigned getBundleSize() const; -- cgit v1.1 From ff2b99afc8cbc6cfa73181072888e0f9f07deb7e Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 9 Aug 2012 22:49:37 +0000 Subject: Move use list management into MachineRegisterInfo. Register MachineOperands are kept in linked lists accessible via MRI's reg_iterator interfaces. The linked list management was handled partly by MachineOperand methods, partly by MRI methods. Move all of the list management into MRI, delete MO::AddRegOperandToRegInfo() and MO::RemoveRegOperandFromRegInfo(). Be more explicit about handling the cases where an MRI pointer isn't available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161632 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen/MachineInstr.h') diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 30433a2..4c5eb8b 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -936,12 +936,12 @@ private: /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in /// this instruction from their respective use lists. This requires that the /// operands already be on their use lists. - void RemoveRegOperandsFromUseLists(); + void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); /// AddRegOperandsToUseLists - Add all of the register operands in /// this instruction from their respective use lists. This requires that the /// operands not be on their use lists yet. - void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo); + void AddRegOperandsToUseLists(MachineRegisterInfo&); /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a /// bundle. -- cgit v1.1 From f2c64ef519b38a4328809b27b4a3a8e0c26e9709 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 16 Aug 2012 23:11:47 +0000 Subject: Add an MCID::Select flag and TII hooks for optimizing selects. Select instructions pick one of two virtual registers based on a condition, like x86 cmov. On targets like ARM that support predication, selects can sometimes be eliminated by predicating the instruction defining one of the operands. Teach PeepholeOptimizer to recognize select instructions, and ask the target to optimize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/llvm/CodeGen/MachineInstr.h') diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 4c5eb8b..27756ab 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -420,6 +420,12 @@ public: return hasProperty(MCID::Bitcast, Type); } + /// isSelect - Return true if this instruction is a select instruction. + /// + bool isSelect(QueryType Type = IgnoreBundle) const { + return hasProperty(MCID::Select, Type); + } + /// isNotDuplicable - Return true if this instruction cannot be safely /// duplicated. For example, if the instruction has a unique labels attached /// to it, duplicating it would cause multiple definition errors. -- cgit v1.1