From 1144af3c9b4da48cd581156e05b24261c8de366a Mon Sep 17 00:00:00 2001 From: Richard Smith Date: Fri, 24 Aug 2012 23:29:28 +0000 Subject: Fix integer undefined behavior due to signed left shift overflow in LLVM. Reviewed offline by chandlerc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineOperand.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen/MachineOperand.h') diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index 37d42b3..c09d9f1 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -421,7 +421,7 @@ public: int64_t getOffset() const { assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && "Wrong MachineOperand accessor"); - return (int64_t(Contents.OffsetedInfo.OffsetHi) << 32) | + return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) | SmallContents.OffsetLo; } -- cgit v1.1 From 190e342cbcb1456ebb21b53a35cfefa99435bd65 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 28 Aug 2012 18:05:48 +0000 Subject: Don't allow TargetFlags on MO_Register MachineOperands. Register operands are manipulated by a lot of target-independent code, and it is not always possible to preserve target flags. That means it is not safe to use target flags on register operands. None of the targets in the tree are using register operand target flags. External targets should be using immediate operands to annotate instructions with operand modifiers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162770 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineOperand.h | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) (limited to 'include/llvm/CodeGen/MachineOperand.h') diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index c09d9f1..1d3d60b 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -60,12 +60,15 @@ private: /// union. unsigned char OpKind; // MachineOperandType - /// SubReg - Subregister number, only valid for MO_Register. A value of 0 - /// indicates the MO_Register has no subReg. - unsigned char SubReg; + // This union is discriminated by OpKind. + union { + /// SubReg - Subregister number, only valid for MO_Register. A value of 0 + /// indicates the MO_Register has no subReg. + unsigned char SubReg; - /// TargetFlags - This is a set of target-specific operand flags. - unsigned char TargetFlags; + /// TargetFlags - This is a set of target-specific operand flags. + unsigned char TargetFlags; + }; /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register /// operands. @@ -176,9 +179,17 @@ public: /// MachineOperandType getType() const { return (MachineOperandType)OpKind; } - unsigned char getTargetFlags() const { return TargetFlags; } - void setTargetFlags(unsigned char F) { TargetFlags = F; } - void addTargetFlag(unsigned char F) { TargetFlags |= F; } + unsigned char getTargetFlags() const { + return isReg() ? 0 : TargetFlags; + } + void setTargetFlags(unsigned char F) { + assert(!isReg() && "Register operands can't have target flags"); + TargetFlags = F; + } + void addTargetFlag(unsigned char F) { + assert(!isReg() && "Register operands can't have target flags"); + TargetFlags |= F; + } /// getParent - Return the instruction that this operand belongs to. -- cgit v1.1 From 4ba6916a98fffd9dedac5945ac51d40c8948069e Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 28 Aug 2012 18:34:41 +0000 Subject: Add a MachineOperand::isTied() flag. While in SSA form, a MachineInstr can have pairs of tied defs and uses. The tied operands are used to represent read-modify-write operands that must be assigned the same physical register. Previously, tied operand pairs were computed from fixed MCInstrDesc fields, or by using black magic on inline assembly instructions. The isTied flag makes it possible to add tied operands to any instruction while getting rid of (some of) the inlineasm magic. Tied operands on normal instructions are needed to represent predicated individual instructions in SSA form. An extra operand is required to represent the output value when the instruction predicate is false. Adding a predicate to: %vreg0 = ADD %vreg1, %vreg2 Will look like: %vreg0 = ADD %vreg1, %vreg2, pred:3, %vreg7 The virtual register %vreg7 is the value given to %vreg0 when the predicate is false. It will be assigned the same physreg as %vreg0. This commit adds the isTied flag and sets it based on MCInstrDesc when building an instruction. The flag is not used for anything yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162774 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineOperand.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include/llvm/CodeGen/MachineOperand.h') diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index 1d3d60b..594dc27 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -124,6 +124,14 @@ private: /// model the GCC inline asm '&' constraint modifier. bool IsEarlyClobber : 1; + /// IsTied - True if this MO_Register operand is tied to another operand on + /// the instruction. Tied operands form def-use pairs that must be assigned + /// the same physical register by the register allocator, but they will have + /// different virtual registers while the code is in SSA form. + /// + /// See MachineInstr::isRegTiedToUseOperand() and isRegTiedToDefOperand(). + bool IsTied : 1; + /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, /// not a real instruction. Such uses should be ignored during codegen. bool IsDebug : 1; @@ -299,6 +307,11 @@ public: return IsEarlyClobber; } + bool isTied() const { + assert(isReg() && "Wrong MachineOperand accessor"); + return IsTied; + } + bool isDebug() const { assert(isReg() && "Wrong MachineOperand accessor"); return IsDebug; @@ -377,6 +390,11 @@ public: IsEarlyClobber = Val; } + void setIsTied(bool Val = true) { + assert(isReg() && "Wrong MachineOperand accessor"); + IsTied = Val; + } + void setIsDebug(bool Val = true) { assert(isReg() && IsDef && "Wrong MachineOperand accessor"); IsDebug = Val; @@ -559,6 +577,7 @@ public: Op.IsUndef = isUndef; Op.IsInternalRead = isInternalRead; Op.IsEarlyClobber = isEarlyClobber; + Op.IsTied = false; Op.IsDebug = isDebug; Op.SmallContents.RegNo = Reg; Op.Contents.Reg.Prev = 0; -- cgit v1.1 From 94083149fd6891c8a72472cf1814fa6600a75979 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 31 Aug 2012 20:50:53 +0000 Subject: Add MachineInstr::tieOperands, remove setIsTied(). Manage tied operands entirely internally to MachineInstr. This makes it possible to change the representation of tied operands, as I will do shortly. The constraint that tied uses and defs must be in the same order was too restrictive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163021 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineOperand.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include/llvm/CodeGen/MachineOperand.h') diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index 594dc27..baec882 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -390,11 +390,6 @@ public: IsEarlyClobber = Val; } - void setIsTied(bool Val = true) { - assert(isReg() && "Wrong MachineOperand accessor"); - IsTied = Val; - } - void setIsDebug(bool Val = true) { assert(isReg() && IsDef && "Wrong MachineOperand accessor"); IsDebug = Val; -- cgit v1.1 From 9c130672761e006c47ea23b34a7bd414f2cd8368 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 4 Sep 2012 18:36:28 +0000 Subject: Allow tied uses and defs in different orders. After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineOperand.h | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'include/llvm/CodeGen/MachineOperand.h') diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index baec882..5c6662e 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -70,6 +70,11 @@ private: unsigned char TargetFlags; }; + /// TiedTo - Non-zero when this register operand is tied to another register + /// operand. The encoding of this field is described in the block comment + /// before MachineInstr::tieOperands(). + unsigned char TiedTo : 4; + /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register /// operands. @@ -124,14 +129,6 @@ private: /// model the GCC inline asm '&' constraint modifier. bool IsEarlyClobber : 1; - /// IsTied - True if this MO_Register operand is tied to another operand on - /// the instruction. Tied operands form def-use pairs that must be assigned - /// the same physical register by the register allocator, but they will have - /// different virtual registers while the code is in SSA form. - /// - /// See MachineInstr::isRegTiedToUseOperand() and isRegTiedToDefOperand(). - bool IsTied : 1; - /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, /// not a real instruction. Such uses should be ignored during codegen. bool IsDebug : 1; @@ -309,7 +306,7 @@ public: bool isTied() const { assert(isReg() && "Wrong MachineOperand accessor"); - return IsTied; + return TiedTo; } bool isDebug() const { @@ -572,7 +569,7 @@ public: Op.IsUndef = isUndef; Op.IsInternalRead = isInternalRead; Op.IsEarlyClobber = isEarlyClobber; - Op.IsTied = false; + Op.TiedTo = 0; Op.IsDebug = isDebug; Op.SmallContents.RegNo = Reg; Op.Contents.Reg.Prev = 0; -- cgit v1.1 From b985e9aacdd604a5a503496a1633fa9c6ef7235c Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 5 Sep 2012 18:19:08 +0000 Subject: Clean up includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163229 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineOperand.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen/MachineOperand.h') diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index 5c6662e..0b9d67f 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -14,7 +14,6 @@ #ifndef LLVM_CODEGEN_MACHINEOPERAND_H #define LLVM_CODEGEN_MACHINEOPERAND_H -#include "llvm/ADT/Hashing.h" #include "llvm/Support/DataTypes.h" #include @@ -30,6 +29,7 @@ class MachineRegisterInfo; class MDNode; class TargetMachine; class TargetRegisterInfo; +class hash_code; class raw_ostream; class MCSymbol; -- cgit v1.1