From 9bf386ea630d7850b5e4cc140e7f47ad07c8e765 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 28 Jul 2008 22:18:25 +0000 Subject: Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, which is represented in codegen as an 'and' operation. This matches them with movz instructions, instead of leaving them to be matched by and instructions with an immediate field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGNodes.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/llvm/CodeGen/SelectionDAGNodes.h') diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index dbb1294..73edcb8 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -377,6 +377,8 @@ namespace ISD { // extending the low 8 bits of a 32-bit register to fill the top 24 bits // with the 7th bit). The size of the smaller type is indicated by the 1th // operand, a ValueType node. + // Note that there is intentionally no corresponding ZERO_EXTEND_INREG; an + // AND with an appropriate constant is used instead. SIGN_EXTEND_INREG, /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned -- cgit v1.1