From d4786e221c679fced994993d9ee7228572d4b148 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 20 Apr 2012 20:05:19 +0000 Subject: Allow converting MachineBasicBlock::iterator to const_iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155225 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineBasicBlock.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index ef9c0c2..18df69e 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -156,7 +156,10 @@ public: assert((!mi || !mi->isInsideBundle()) && "It's not legal to initialize bundle_iterator with a bundled MI"); } - bundle_iterator(const bundle_iterator &I) : MII(I.MII) {} + // Template allows conversion from const to nonconst. + template + bundle_iterator(const bundle_iterator &I) + : MII(I.getInstrIterator()) {} bundle_iterator() : MII(0) {} Ty &operator*() const { return *MII; } -- cgit v1.1 From c0ccb8bb17028fe0dda139c0972c0125d10e6053 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Fri, 20 Apr 2012 20:05:28 +0000 Subject: SparseSet: Add support for key-derived indexes and arbitrary key types. This nicely handles the most common case of virtual register sets, but also handles anticipated cases where we will map pointers to IDs. The goal is not to develop a completely generic SparseSet template. Instead we want to handle the expected uses within llvm without any template antics in the client code. I'm adding a bit of template nastiness here, and some assumption about expected usage in order to make the client code very clean. The expected common uses cases I'm designing for: - integer keys that need to be reindexed, and may map to additional data - densely numbered objects where we want pointer keys because no number->object map exists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155227 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAGInstrs.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index 4fee108..766c9b2 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -105,7 +105,7 @@ namespace llvm { VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} - unsigned getSparseSetKey() const { + unsigned getSparseSetIndex() const { return TargetRegisterInfo::virtReg2Index(VirtReg); } }; @@ -160,7 +160,7 @@ namespace llvm { /// compares ValueT's, only unsigned keys. This allows the set to be cleared /// between scheduling regions in constant time as long as ValueT does not /// require a destructor. - typedef SparseSet VReg2SUnitMap; + typedef SparseSet VReg2SUnitMap; /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of /// MachineInstrs. @@ -321,10 +321,6 @@ namespace llvm { void addPhysRegDeps(SUnit *SU, unsigned OperIdx); void addVRegDefDeps(SUnit *SU, unsigned OperIdx); void addVRegUseDeps(SUnit *SU, unsigned OperIdx); - - VReg2SUnitMap::iterator findVRegDef(unsigned VirtReg) { - return VRegDefs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); - } }; /// newSUnit - Creates a new SUnit and return a ptr to it. -- cgit v1.1 From bc7d448f242b1bbc1031fb87cd69c285ff9aaffa Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 20 Apr 2012 22:08:46 +0000 Subject: Register DAGUpdateListeners with SelectionDAG. Instead of passing listener pointers to RAUW, let SelectionDAG itself keep a linked list of interested listeners. This makes it possible to have multiple listeners active at once, like RAUWUpdateListener was already doing. It also makes it possible to register listeners up the call stack without controlling all RAUW calls below. DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG list of active listeners. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155248 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAG.h | 75 ++++++++++++++++++++------------- include/llvm/CodeGen/SelectionDAGISel.h | 19 ++++----- 2 files changed, 54 insertions(+), 40 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index 6a7a87e..a5a912a 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -177,6 +177,44 @@ class SelectionDAG { /// DbgInfo - Tracks dbg_value information through SDISel. SDDbgInfo *DbgInfo; +public: + /// DAGUpdateListener - Clients of various APIs that cause global effects on + /// the DAG can optionally implement this interface. This allows the clients + /// to handle the various sorts of updates that happen. + /// + /// A DAGUpdateListener automatically registers itself with DAG when it is + /// constructed, and removes itself when destroyed in RAII fashion. + struct DAGUpdateListener { + DAGUpdateListener *const Next; + SelectionDAG &DAG; + + explicit DAGUpdateListener(SelectionDAG &D) + : Next(D.UpdateListeners), DAG(D) { + DAG.UpdateListeners = this; + } + + virtual ~DAGUpdateListener() { + assert(DAG.UpdateListeners == this && + "DAGUpdateListeners must be destroyed in LIFO order"); + DAG.UpdateListeners = Next; + } + + /// NodeDeleted - The node N that was deleted and, if E is not null, an + /// equivalent node E that replaced it. + virtual void NodeDeleted(SDNode *N, SDNode *E); + + /// NodeUpdated - The node N that was updated. + virtual void NodeUpdated(SDNode *N); + }; + +private: + /// DAGUpdateListener is a friend so it can manipulate the listener stack. + friend struct DAGUpdateListener; + + /// UpdateListeners - Linked list of registered DAGUpdateListener instances. + /// This stack is maintained by DAGUpdateListener RAII. + DAGUpdateListener *UpdateListeners; + /// setGraphColorHelper - Implementation of setSubgraphColor. /// Return whether we had to truncate the search. /// @@ -817,30 +855,14 @@ public: SDDbgValue *getDbgValue(MDNode *MDPtr, unsigned FI, uint64_t Off, DebugLoc DL, unsigned O); - /// DAGUpdateListener - Clients of various APIs that cause global effects on - /// the DAG can optionally implement this interface. This allows the clients - /// to handle the various sorts of updates that happen. - class DAGUpdateListener { - public: - virtual ~DAGUpdateListener(); - - /// NodeDeleted - The node N that was deleted and, if E is not null, an - /// equivalent node E that replaced it. - virtual void NodeDeleted(SDNode *N, SDNode *E) = 0; - - /// NodeUpdated - The node N that was updated. - virtual void NodeUpdated(SDNode *N) = 0; - }; - /// RemoveDeadNode - Remove the specified node from the system. If any of its /// operands then becomes dead, remove them as well. Inform UpdateListener /// for each node deleted. - void RemoveDeadNode(SDNode *N, DAGUpdateListener *UpdateListener = 0); + void RemoveDeadNode(SDNode *N); /// RemoveDeadNodes - This method deletes the unreachable nodes in the /// given list, and any nodes that become unreachable as a result. - void RemoveDeadNodes(SmallVectorImpl &DeadNodes, - DAGUpdateListener *UpdateListener = 0); + void RemoveDeadNodes(SmallVectorImpl &DeadNodes); /// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. /// This can cause recursive merging of nodes in the DAG. Use the first @@ -857,24 +879,19 @@ public: /// to be given new uses. These new uses of From are left in place, and /// not automatically transferred to To. /// - void ReplaceAllUsesWith(SDValue From, SDValue Op, - DAGUpdateListener *UpdateListener = 0); - void ReplaceAllUsesWith(SDNode *From, SDNode *To, - DAGUpdateListener *UpdateListener = 0); - void ReplaceAllUsesWith(SDNode *From, const SDValue *To, - DAGUpdateListener *UpdateListener = 0); + void ReplaceAllUsesWith(SDValue From, SDValue Op); + void ReplaceAllUsesWith(SDNode *From, SDNode *To); + void ReplaceAllUsesWith(SDNode *From, const SDValue *To); /// ReplaceAllUsesOfValueWith - Replace any uses of From with To, leaving /// uses of other values produced by From.Val alone. - void ReplaceAllUsesOfValueWith(SDValue From, SDValue To, - DAGUpdateListener *UpdateListener = 0); + void ReplaceAllUsesOfValueWith(SDValue From, SDValue To); /// ReplaceAllUsesOfValuesWith - Like ReplaceAllUsesOfValueWith, but /// for multiple values at once. This correctly handles the case where /// there is an overlap between the From values and the To values. void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, - unsigned Num, - DAGUpdateListener *UpdateListener = 0); + unsigned Num); /// AssignTopologicalOrder - Topological-sort the AllNodes list and a /// assign a unique node id for each node in the DAG based on their @@ -1031,7 +1048,7 @@ public: private: bool RemoveNodeFromCSEMaps(SDNode *N); - void AddModifiedNodeToCSEMaps(SDNode *N, DAGUpdateListener *UpdateListener); + void AddModifiedNodeToCSEMaps(SDNode *N); SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos); SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2, void *&InsertPos); diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index ee3f231..6829a57 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -184,8 +184,8 @@ protected: virtual void anchor(); SelectionDAG::allnodes_iterator &ISelPosition; public: - explicit ISelUpdater(SelectionDAG::allnodes_iterator &isp) - : ISelPosition(isp) {} + ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) + : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} /// NodeDeleted - Handle nodes deleted from the graph. If the /// node being deleted is the current ISelPosition node, update @@ -195,30 +195,27 @@ protected: if (ISelPosition == SelectionDAG::allnodes_iterator(N)) ++ISelPosition; } - - /// NodeUpdated - Ignore updates for now. - virtual void NodeUpdated(SDNode *N) {} }; /// ReplaceUses - replace all uses of the old node F with the use /// of the new node T. void ReplaceUses(SDValue F, SDValue T) { - ISelUpdater ISU(ISelPosition); - CurDAG->ReplaceAllUsesOfValueWith(F, T, &ISU); + ISelUpdater ISU(*CurDAG, ISelPosition); + CurDAG->ReplaceAllUsesOfValueWith(F, T); } /// ReplaceUses - replace all uses of the old nodes F with the use /// of the new nodes T. void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { - ISelUpdater ISU(ISelPosition); - CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num, &ISU); + ISelUpdater ISU(*CurDAG, ISelPosition); + CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); } /// ReplaceUses - replace all uses of the old node F with the use /// of the new node T. void ReplaceUses(SDNode *F, SDNode *T) { - ISelUpdater ISU(ISelPosition); - CurDAG->ReplaceAllUsesWith(F, T, &ISU); + ISelUpdater ISU(*CurDAG, ISelPosition); + CurDAG->ReplaceAllUsesWith(F, T); } -- cgit v1.1 From 8c48e4ff899303eb9a4ea8ed1c43d175f0cf48ff Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 20 Apr 2012 22:08:50 +0000 Subject: Make ISelPosition a local variable. Now that multiple DAGUpdateListeners can be active at the same time, ISelPosition can become a local variable in DoInstructionSelection. We simply register an ISelUpdater with CurDAG while ISelPosition exists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155249 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGISel.h | 28 ---------------------------- 1 file changed, 28 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 6829a57..c42f655 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -172,49 +172,21 @@ protected: /// unsigned DAGSize; - /// ISelPosition - Node iterator marking the current position of - /// instruction selection as it procedes through the topologically-sorted - /// node list. - SelectionDAG::allnodes_iterator ISelPosition; - - - /// ISelUpdater - helper class to handle updates of the - /// instruction selection graph. - class ISelUpdater : public SelectionDAG::DAGUpdateListener { - virtual void anchor(); - SelectionDAG::allnodes_iterator &ISelPosition; - public: - ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) - : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} - - /// NodeDeleted - Handle nodes deleted from the graph. If the - /// node being deleted is the current ISelPosition node, update - /// ISelPosition. - /// - virtual void NodeDeleted(SDNode *N, SDNode *E) { - if (ISelPosition == SelectionDAG::allnodes_iterator(N)) - ++ISelPosition; - } - }; - /// ReplaceUses - replace all uses of the old node F with the use /// of the new node T. void ReplaceUses(SDValue F, SDValue T) { - ISelUpdater ISU(*CurDAG, ISelPosition); CurDAG->ReplaceAllUsesOfValueWith(F, T); } /// ReplaceUses - replace all uses of the old nodes F with the use /// of the new nodes T. void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { - ISelUpdater ISU(*CurDAG, ISelPosition); CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); } /// ReplaceUses - replace all uses of the old node F with the use /// of the new node T. void ReplaceUses(SDNode *F, SDNode *T) { - ISelUpdater ISU(*CurDAG, ISelPosition); CurDAG->ReplaceAllUsesWith(F, T); } -- cgit v1.1 From 0b5ad0b9d902620b81268add3f554d73a6d92fc1 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 21 Apr 2012 16:05:27 +0000 Subject: Remove unused PointerLikeTypeTraits for IndexListEntry. It set NumLowBitAvailable = 3 which may not be true on all platforms. We only ever use 2 bits (the default) so this assumption can be safely removed Should fix PR12612. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155288 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SlotIndexes.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/SlotIndexes.h b/include/llvm/CodeGen/SlotIndexes.h index dfea0ac..0457e43 100644 --- a/include/llvm/CodeGen/SlotIndexes.h +++ b/include/llvm/CodeGen/SlotIndexes.h @@ -73,19 +73,6 @@ namespace llvm { void createNode(const IndexListEntry &); }; - // Specialize PointerLikeTypeTraits for IndexListEntry. - template <> - class PointerLikeTypeTraits { - public: - static inline void* getAsVoidPointer(IndexListEntry *p) { - return p; - } - static inline IndexListEntry* getFromVoidPointer(void *p) { - return static_cast(p); - } - enum { NumLowBitsAvailable = 3 }; - }; - /// SlotIndex - An opaque wrapper around machine indexes. class SlotIndex { friend class SlotIndexes; -- cgit v1.1 From 9f6852dcc292882845876ecc1181710a5c35fb1f Mon Sep 17 00:00:00 2001 From: Sirish Pande Date: Mon, 23 Apr 2012 17:49:09 +0000 Subject: Hexagon Packetizer's target independent fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155364 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/DFAPacketizer.h | 44 ++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 12 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index ee1ed07..2d2db78 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/ADT/DenseMap.h" +#include namespace llvm { @@ -36,7 +37,7 @@ class MachineInstr; class MachineLoopInfo; class MachineDominatorTree; class InstrItineraryData; -class ScheduleDAGInstrs; +class DefaultVLIWScheduler; class SUnit; class DFAPacketizer { @@ -77,6 +78,8 @@ public: // reserveResources - Reserve the resources occupied by a machine // instruction and change the current state to reflect that change. void reserveResources(llvm::MachineInstr *MI); + + const InstrItineraryData *getInstrItins() const { return InstrItins; } }; // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The @@ -87,20 +90,21 @@ public: // and machine resource is marked as taken. If any dependency is found, a target // API call is made to prune the dependence. class VLIWPacketizerList { +protected: const TargetMachine &TM; const MachineFunction &MF; const TargetInstrInfo *TII; - // Encapsulate data types not exposed to the target interface. - ScheduleDAGInstrs *SchedulerImpl; + // The VLIW Scheduler. + DefaultVLIWScheduler *VLIWScheduler; -protected: // Vector of instructions assigned to the current packet. std::vector CurrentPacketMIs; // DFA resource tracker. DFAPacketizer *ResourceTracker; - // Scheduling units. - std::vector SUnits; + + // Generate MI -> SU map. + std::map MIToSUnit; public: VLIWPacketizerList( @@ -118,17 +122,32 @@ public: DFAPacketizer *getResourceTracker() {return ResourceTracker;} // addToPacket - Add MI to the current packet. - void addToPacket(MachineInstr *MI); + virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) { + MachineBasicBlock::iterator MII = MI; + CurrentPacketMIs.push_back(MI); + ResourceTracker->reserveResources(MI); + return MII; + } // endPacket - End the current packet. - void endPacket(MachineBasicBlock *MBB, MachineInstr *I); + void endPacket(MachineBasicBlock *MBB, MachineInstr *MI); + + // initPacketizerState - perform initialization before packetizing + // an instruction. This function is supposed to be overrided by + // the target dependent packetizer. + virtual void initPacketizerState(void) { return; } // ignorePseudoInstruction - Ignore bundling of pseudo instructions. - bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB); + virtual bool ignorePseudoInstruction(MachineInstr *I, + MachineBasicBlock *MBB) { + return false; + } - // isSoloInstruction - return true if instruction I must end previous - // packet. - bool isSoloInstruction(MachineInstr *I); + // isSoloInstruction - return true if instruction MI can not be packetized + // with any other instruction, which means that MI itself is a packet. + virtual bool isSoloInstruction(MachineInstr *MI) { + return true; + } // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // together. @@ -141,6 +160,7 @@ public: virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { return false; } + }; } -- cgit v1.1 From e3fd2a36d93ed65fabe9cd8e1c98edd8d4f7ec62 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Mon, 23 Apr 2012 18:28:57 +0000 Subject: Temporarily revert r155364 until the upstream review can complete, per the stated developer policy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155373 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/DFAPacketizer.h | 44 ++++++++++-------------------------- 1 file changed, 12 insertions(+), 32 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index 2d2db78..ee1ed07 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -28,7 +28,6 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/ADT/DenseMap.h" -#include namespace llvm { @@ -37,7 +36,7 @@ class MachineInstr; class MachineLoopInfo; class MachineDominatorTree; class InstrItineraryData; -class DefaultVLIWScheduler; +class ScheduleDAGInstrs; class SUnit; class DFAPacketizer { @@ -78,8 +77,6 @@ public: // reserveResources - Reserve the resources occupied by a machine // instruction and change the current state to reflect that change. void reserveResources(llvm::MachineInstr *MI); - - const InstrItineraryData *getInstrItins() const { return InstrItins; } }; // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The @@ -90,21 +87,20 @@ public: // and machine resource is marked as taken. If any dependency is found, a target // API call is made to prune the dependence. class VLIWPacketizerList { -protected: const TargetMachine &TM; const MachineFunction &MF; const TargetInstrInfo *TII; - // The VLIW Scheduler. - DefaultVLIWScheduler *VLIWScheduler; + // Encapsulate data types not exposed to the target interface. + ScheduleDAGInstrs *SchedulerImpl; +protected: // Vector of instructions assigned to the current packet. std::vector CurrentPacketMIs; // DFA resource tracker. DFAPacketizer *ResourceTracker; - - // Generate MI -> SU map. - std::map MIToSUnit; + // Scheduling units. + std::vector SUnits; public: VLIWPacketizerList( @@ -122,32 +118,17 @@ public: DFAPacketizer *getResourceTracker() {return ResourceTracker;} // addToPacket - Add MI to the current packet. - virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) { - MachineBasicBlock::iterator MII = MI; - CurrentPacketMIs.push_back(MI); - ResourceTracker->reserveResources(MI); - return MII; - } + void addToPacket(MachineInstr *MI); // endPacket - End the current packet. - void endPacket(MachineBasicBlock *MBB, MachineInstr *MI); - - // initPacketizerState - perform initialization before packetizing - // an instruction. This function is supposed to be overrided by - // the target dependent packetizer. - virtual void initPacketizerState(void) { return; } + void endPacket(MachineBasicBlock *MBB, MachineInstr *I); // ignorePseudoInstruction - Ignore bundling of pseudo instructions. - virtual bool ignorePseudoInstruction(MachineInstr *I, - MachineBasicBlock *MBB) { - return false; - } + bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB); - // isSoloInstruction - return true if instruction MI can not be packetized - // with any other instruction, which means that MI itself is a packet. - virtual bool isSoloInstruction(MachineInstr *MI) { - return true; - } + // isSoloInstruction - return true if instruction I must end previous + // packet. + bool isSoloInstruction(MachineInstr *I); // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // together. @@ -160,7 +141,6 @@ public: virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { return false; } - }; } -- cgit v1.1 From 006e1abf76148626fb38de1b643c2d31de7f08a7 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Tue, 24 Apr 2012 17:56:43 +0000 Subject: misched: DAG builder support for tracking register pressure within the current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155456 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineScheduler.h | 6 +++++- include/llvm/CodeGen/ScheduleDAGInstrs.h | 3 ++- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h index 474c95d..a7ed0bd 100644 --- a/include/llvm/CodeGen/MachineScheduler.h +++ b/include/llvm/CodeGen/MachineScheduler.h @@ -27,6 +27,7 @@ #ifndef MACHINESCHEDULER_H #define MACHINESCHEDULER_H +#include "RegisterClassInfo.h" #include "llvm/CodeGen/MachinePassRegistry.h" namespace llvm { @@ -47,7 +48,10 @@ struct MachineSchedContext { AliasAnalysis *AA; LiveIntervals *LIS; - MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {} + RegisterClassInfo RegClassInfo; + + MachineSchedContext(): + MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {} }; /// MachineSchedRegistry provides a selection of available machine instruction diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index 766c9b2..dcf72c7 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -28,6 +28,7 @@ namespace llvm { class MachineLoopInfo; class MachineDominatorTree; class LiveIntervals; + class RegPressureTracker; /// LoopDependencies - This class analyzes loop-oriented register /// dependencies, which are used to guide scheduling decisions. @@ -275,7 +276,7 @@ namespace llvm { /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are /// input. - void buildSchedGraph(AliasAnalysis *AA); + void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker = 0); /// addSchedBarrierDeps - Add dependencies from instructions in the current /// list of instructions being scheduled to scheduling barrier. We want to -- cgit v1.1 From 86b7e2acc9e3b55b8afdfeabda124cc6547e943b Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Tue, 24 Apr 2012 20:36:19 +0000 Subject: Fix a naughty header include that breaks "installed" builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155486 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineScheduler.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h index a7ed0bd..b0b6aa7 100644 --- a/include/llvm/CodeGen/MachineScheduler.h +++ b/include/llvm/CodeGen/MachineScheduler.h @@ -27,7 +27,6 @@ #ifndef MACHINESCHEDULER_H #define MACHINESCHEDULER_H -#include "RegisterClassInfo.h" #include "llvm/CodeGen/MachinePassRegistry.h" namespace llvm { @@ -36,6 +35,7 @@ class AliasAnalysis; class LiveIntervals; class MachineDominatorTree; class MachineLoopInfo; +class RegClassInfo; class ScheduleDAGInstrs; /// MachineSchedContext provides enough context from the MachineScheduler pass @@ -48,10 +48,10 @@ struct MachineSchedContext { AliasAnalysis *AA; LiveIntervals *LIS; - RegisterClassInfo RegClassInfo; + RegisterClassInfo *RegClassInfo; - MachineSchedContext(): - MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {} + MachineSchedContext(); + virtual ~MachineSchedContext(); }; /// MachineSchedRegistry provides a selection of available machine instruction -- cgit v1.1 From 23d59c2fb847f1869b72bcbda67052ac6b2aaee9 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 25 Apr 2012 01:11:22 +0000 Subject: typo in declaration from earlier today git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155519 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineScheduler.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h index b0b6aa7..e5d3a98 100644 --- a/include/llvm/CodeGen/MachineScheduler.h +++ b/include/llvm/CodeGen/MachineScheduler.h @@ -35,7 +35,7 @@ class AliasAnalysis; class LiveIntervals; class MachineDominatorTree; class MachineLoopInfo; -class RegClassInfo; +class RegisterClassInfo; class ScheduleDAGInstrs; /// MachineSchedContext provides enough context from the MachineScheduler pass -- cgit v1.1 From a62efd82ccb979df9e7b8f99913c83d698a6994e Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 25 Apr 2012 16:32:20 +0000 Subject: Remove a dead function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155553 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 76201c9..9329338 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -144,12 +144,6 @@ namespace llvm { return (1000.0 * I.getSize()) / indexes_->getIndexesLength(); } - /// getFuncInstructionCount - Return the number of instructions in the - /// current function. - unsigned getFuncInstructionCount() { - return indexes_->getFunctionSize(); - } - /// getApproximateInstructionCount - computes an estimate of the number /// of instructions in a given LiveInterval. unsigned getApproximateInstructionCount(LiveInterval& I) { -- cgit v1.1 From 50e1d84ba8efc1973137c65e0b0e048ecf8cf5d6 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 25 Apr 2012 16:32:23 +0000 Subject: Simplify LiveIntervals::getApproximateInstructionCount(). This function is only used for a heuristic during -join-physregs. It doesn't need floating point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155554 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 9329338..c3c6e2d 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -147,8 +147,7 @@ namespace llvm { /// getApproximateInstructionCount - computes an estimate of the number /// of instructions in a given LiveInterval. unsigned getApproximateInstructionCount(LiveInterval& I) { - double IntervalPercentage = getScaledIntervalSize(I) / 1000.0; - return (unsigned)(IntervalPercentage * indexes_->getFunctionSize()); + return I.getSize()/SlotIndex::InstrDist; } // Interval creation -- cgit v1.1 From a0b0219a9e13ecd193eee604ab22ffc74b516b02 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 25 Apr 2012 18:01:30 +0000 Subject: Remove more dead code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155566 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 7 ------- include/llvm/CodeGen/SlotIndexes.h | 14 -------------- 2 files changed, 21 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index c3c6e2d..3cc31ad 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -137,13 +137,6 @@ namespace llvm { return reservedRegs_.test(reg); } - /// getScaledIntervalSize - get the size of an interval in "units," - /// where every function is composed of one thousand units. This - /// measure scales properly with empty index slots in the function. - double getScaledIntervalSize(LiveInterval& I) { - return (1000.0 * I.getSize()) / indexes_->getIndexesLength(); - } - /// getApproximateInstructionCount - computes an estimate of the number /// of instructions in a given LiveInterval. unsigned getApproximateInstructionCount(LiveInterval& I) { diff --git a/include/llvm/CodeGen/SlotIndexes.h b/include/llvm/CodeGen/SlotIndexes.h index 0457e43..02d64c9 100644 --- a/include/llvm/CodeGen/SlotIndexes.h +++ b/include/llvm/CodeGen/SlotIndexes.h @@ -344,7 +344,6 @@ namespace llvm { IndexList indexList; MachineFunction *mf; - unsigned functionSize; typedef DenseMap Mi2IndexMap; Mi2IndexMap mi2iMap; @@ -402,19 +401,6 @@ namespace llvm { return SlotIndex(&indexList.back(), 0); } - /// Returns the distance between the highest and lowest indexes allocated - /// so far. - unsigned getIndexesLength() const { - assert(indexList.front().getIndex() == 0 && - "Initial index isn't zero?"); - return indexList.back().getIndex(); - } - - /// Returns the number of instructions in the function. - unsigned getFunctionSize() const { - return functionSize; - } - /// Returns true if the given machine instr is mapped to an index, /// otherwise returns false. bool hasIndex(const MachineInstr *instr) const { -- cgit v1.1 From f4aee4c50e2ce46946f71bbb7d7a849b054018f7 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sat, 28 Apr 2012 19:19:07 +0000 Subject: Spring cleaning - Delete dead code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155765 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 24 ------------------------ 1 file changed, 24 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index a6008ab..18096ec 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -288,17 +288,6 @@ namespace llvm { /// unused values. void RenumberValues(LiveIntervals &lis); - /// isOnlyLROfValNo - Return true if the specified live range is the only - /// one defined by the its val#. - bool isOnlyLROfValNo(const LiveRange *LR) { - for (const_iterator I = begin(), E = end(); I != E; ++I) { - const LiveRange *Tmp = I; - if (Tmp != LR && Tmp->valno == LR->valno) - return false; - } - return true; - } - /// MergeValueNumberInto - This method is called when two value nubmers /// are found to be equivalent. This eliminates V1, replacing all /// LiveRanges with the V1 value number with the V2 value number. This can @@ -377,14 +366,6 @@ namespace llvm { return I == end() ? 0 : &*I; } - const LiveRange *getLiveRangeBefore(SlotIndex Idx) const { - return getLiveRangeContaining(Idx.getPrevSlot()); - } - - LiveRange *getLiveRangeBefore(SlotIndex Idx) { - return getLiveRangeContaining(Idx.getPrevSlot()); - } - /// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL. VNInfo *getVNInfoAt(SlotIndex Idx) const { const_iterator I = FindLiveRangeContaining(Idx); @@ -411,11 +392,6 @@ namespace llvm { return I != end() && I->start <= Idx ? I : end(); } - /// findDefinedVNInfo - Find the by the specified - /// index (register interval) or defined - VNInfo *findDefinedVNInfoForRegInt(SlotIndex Idx) const; - - /// overlaps - Return true if the intersection of the two live intervals is /// not empty. bool overlaps(const LiveInterval& other) const { -- cgit v1.1 From ff11c0185391023d4f7b3254de94e11a5bb9cd58 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sat, 28 Apr 2012 19:19:11 +0000 Subject: Don't update spill weights when joining intervals. We don't compute spill weights until after coalescing anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155766 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 18096ec..3170952 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -474,10 +474,6 @@ namespace llvm { weight = HUGE_VALF; } - /// ComputeJoinedWeight - Set the weight of a live interval after - /// Other has been merged into it. - void ComputeJoinedWeight(const LiveInterval &Other); - bool operator<(const LiveInterval& other) const { const SlotIndex &thisIndex = beginIndex(); const SlotIndex &otherIndex = other.beginIndex(); -- cgit v1.1 From 9efb030911d05ca4a913a1179f3f5b7d04ae5077 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 29 Apr 2012 07:06:58 +0000 Subject: Mark the default cases of MVT::getVectorElementType and MVT:getVectorNumElements as unreachable to reduce code size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155785 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ValueTypes.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h index 76c2357..caeca17 100644 --- a/include/llvm/CodeGen/ValueTypes.h +++ b/include/llvm/CodeGen/ValueTypes.h @@ -196,7 +196,7 @@ namespace llvm { MVT getVectorElementType() const { switch (SimpleTy) { default: - return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE); + llvm_unreachable("Not a vector MVT!"); case v2i8 : case v4i8 : case v8i8 : @@ -225,7 +225,7 @@ namespace llvm { unsigned getVectorNumElements() const { switch (SimpleTy) { default: - return ~0U; + llvm_unreachable("Not a vector MVT!"); case v32i8: return 32; case v16i8: case v16i16: return 16; -- cgit v1.1 From c7f7a9ba7954f0440e696a06de0a2c3c1bcf8a0a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 29 Apr 2012 07:07:36 +0000 Subject: Remove tab characters git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155786 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ValueTypes.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h index caeca17..09e4784 100644 --- a/include/llvm/CodeGen/ValueTypes.h +++ b/include/llvm/CodeGen/ValueTypes.h @@ -153,7 +153,7 @@ namespace llvm { bool isFloatingPoint() const { return ((SimpleTy >= MVT::FIRST_FP_VALUETYPE && SimpleTy <= MVT::LAST_FP_VALUETYPE) || - (SimpleTy >= MVT::FIRST_FP_VECTOR_VALUETYPE && + (SimpleTy >= MVT::FIRST_FP_VECTOR_VALUETYPE && SimpleTy <= MVT::LAST_FP_VECTOR_VALUETYPE)); } @@ -161,7 +161,7 @@ namespace llvm { bool isInteger() const { return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) || - (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64)); + (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64)); } /// isVector - Return true if this is a vector value type. -- cgit v1.1 From db0bbdea472d547b3183d8b365752b3002517407 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 29 Apr 2012 07:25:46 +0000 Subject: Add constants for first and last integer vector types to be consistent with floating point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155787 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ValueTypes.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h index 09e4784..3fdda8a 100644 --- a/include/llvm/CodeGen/ValueTypes.h +++ b/include/llvm/CodeGen/ValueTypes.h @@ -82,6 +82,8 @@ namespace llvm { FIRST_VECTOR_VALUETYPE = v2i8, LAST_VECTOR_VALUETYPE = v4f64, + FIRST_INTEGER_VECTOR_VALUETYPE = v2i8, + LAST_INTEGER_VECTOR_VALUETYPE = v8i64, FIRST_FP_VECTOR_VALUETYPE = v2f16, LAST_FP_VECTOR_VALUETYPE = v4f64, @@ -161,7 +163,8 @@ namespace llvm { bool isInteger() const { return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) || - (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64)); + (SimpleTy >= MVT::FIRST_INTEGER_VECTOR_VALUETYPE && + SimpleTy <= MVT::LAST_INTEGER_VECTOR_VALUETYPE)); } /// isVector - Return true if this is a vector value type. -- cgit v1.1 From 79889819900c077dc17c89cab3cd1b24292aad29 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 29 Apr 2012 20:27:47 +0000 Subject: Remove superfluous 'inline' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155799 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ValueTypes.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h index 3fdda8a..bda43dc 100644 --- a/include/llvm/CodeGen/ValueTypes.h +++ b/include/llvm/CodeGen/ValueTypes.h @@ -506,7 +506,7 @@ namespace llvm { } /// is256BitVector - Return true if this is a 256-bit vector type. - inline bool is256BitVector() const { + bool is256BitVector() const { if (!isSimple()) return isExtended256BitVector(); return (V == MVT::v8f32 || V == MVT::v4f64 || V == MVT::v32i8 || @@ -514,7 +514,7 @@ namespace llvm { } /// is512BitVector - Return true if this is a 512-bit vector type. - inline bool is512BitVector() const { + bool is512BitVector() const { return isSimple() ? (V == MVT::v8i64) : isExtended512BitVector(); } -- cgit v1.1 From 7c4ce30ea6a9d0410f306e805403dd224c3df65c Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Tue, 1 May 2012 08:27:43 +0000 Subject: Change the PassManager from a reference to a pointer. The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 3b38199..e76fe99 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -56,7 +56,7 @@ public: protected: TargetMachine *TM; - PassManagerBase &PM; + PassManagerBase *PM; PassConfigImpl *Impl; // Internal data structures bool Initialized; // Flagged after all passes are configured. -- cgit v1.1 From 902337092fef14ce2519b4c93c37d72bf66ce768 Mon Sep 17 00:00:00 2001 From: Sirish Pande Date: Tue, 1 May 2012 21:28:30 +0000 Subject: Target independent Hexagon Packetizer fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155947 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/DFAPacketizer.h | 44 ++++++++++++++++++++++++++---------- 1 file changed, 32 insertions(+), 12 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index ee1ed07..2d2db78 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -28,6 +28,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/ADT/DenseMap.h" +#include namespace llvm { @@ -36,7 +37,7 @@ class MachineInstr; class MachineLoopInfo; class MachineDominatorTree; class InstrItineraryData; -class ScheduleDAGInstrs; +class DefaultVLIWScheduler; class SUnit; class DFAPacketizer { @@ -77,6 +78,8 @@ public: // reserveResources - Reserve the resources occupied by a machine // instruction and change the current state to reflect that change. void reserveResources(llvm::MachineInstr *MI); + + const InstrItineraryData *getInstrItins() const { return InstrItins; } }; // VLIWPacketizerList - Implements a simple VLIW packetizer using DFA. The @@ -87,20 +90,21 @@ public: // and machine resource is marked as taken. If any dependency is found, a target // API call is made to prune the dependence. class VLIWPacketizerList { +protected: const TargetMachine &TM; const MachineFunction &MF; const TargetInstrInfo *TII; - // Encapsulate data types not exposed to the target interface. - ScheduleDAGInstrs *SchedulerImpl; + // The VLIW Scheduler. + DefaultVLIWScheduler *VLIWScheduler; -protected: // Vector of instructions assigned to the current packet. std::vector CurrentPacketMIs; // DFA resource tracker. DFAPacketizer *ResourceTracker; - // Scheduling units. - std::vector SUnits; + + // Generate MI -> SU map. + std::map MIToSUnit; public: VLIWPacketizerList( @@ -118,17 +122,32 @@ public: DFAPacketizer *getResourceTracker() {return ResourceTracker;} // addToPacket - Add MI to the current packet. - void addToPacket(MachineInstr *MI); + virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) { + MachineBasicBlock::iterator MII = MI; + CurrentPacketMIs.push_back(MI); + ResourceTracker->reserveResources(MI); + return MII; + } // endPacket - End the current packet. - void endPacket(MachineBasicBlock *MBB, MachineInstr *I); + void endPacket(MachineBasicBlock *MBB, MachineInstr *MI); + + // initPacketizerState - perform initialization before packetizing + // an instruction. This function is supposed to be overrided by + // the target dependent packetizer. + virtual void initPacketizerState(void) { return; } // ignorePseudoInstruction - Ignore bundling of pseudo instructions. - bool ignorePseudoInstruction(MachineInstr *I, MachineBasicBlock *MBB); + virtual bool ignorePseudoInstruction(MachineInstr *I, + MachineBasicBlock *MBB) { + return false; + } - // isSoloInstruction - return true if instruction I must end previous - // packet. - bool isSoloInstruction(MachineInstr *I); + // isSoloInstruction - return true if instruction MI can not be packetized + // with any other instruction, which means that MI itself is a packet. + virtual bool isSoloInstruction(MachineInstr *MI) { + return true; + } // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // together. @@ -141,6 +160,7 @@ public: virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { return false; } + }; } -- cgit v1.1 From f09769067fa01d45ddb794aa4af906f6ec2b085e Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 7 May 2012 02:25:53 +0000 Subject: Tidy up. Whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156276 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineJumpTableInfo.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineJumpTableInfo.h b/include/llvm/CodeGen/MachineJumpTableInfo.h index 6bd6682..f7c4e86 100644 --- a/include/llvm/CodeGen/MachineJumpTableInfo.h +++ b/include/llvm/CodeGen/MachineJumpTableInfo.h @@ -10,9 +10,9 @@ // The MachineJumpTableInfo class keeps track of jump tables referenced by // lowered switch instructions in the MachineFunction. // -// Instructions reference the address of these jump tables through the use of -// MO_JumpTableIndex values. When emitting assembly or machine code, these -// virtual address references are converted to refer to the address of the +// Instructions reference the address of these jump tables through the use of +// MO_JumpTableIndex values. When emitting assembly or machine code, these +// virtual address references are converted to refer to the address of the // function jump tables. // //===----------------------------------------------------------------------===// @@ -34,11 +34,11 @@ class raw_ostream; struct MachineJumpTableEntry { /// MBBs - The vector of basic blocks from which to create the jump table. std::vector MBBs; - + explicit MachineJumpTableEntry(const std::vector &M) : MBBs(M) {} }; - + class MachineJumpTableInfo { public: /// JTEntryKind - This enum indicates how each entry of the jump table is @@ -57,7 +57,7 @@ public: /// with a relocation as gp-relative, e.g.: /// .gprel32 LBB123 EK_GPRel32BlockAddress, - + /// EK_LabelDifference32 - Each entry is the address of the block minus /// the address of the jump table. This is used for PIC jump tables where /// gprel32 is not supported. e.g.: @@ -80,18 +80,18 @@ private: std::vector JumpTables; public: explicit MachineJumpTableInfo(JTEntryKind Kind): EntryKind(Kind) {} - + JTEntryKind getEntryKind() const { return EntryKind; } /// getEntrySize - Return the size of each entry in the jump table. unsigned getEntrySize(const TargetData &TD) const; /// getEntryAlignment - Return the alignment of each entry in the jump table. unsigned getEntryAlignment(const TargetData &TD) const; - + /// createJumpTableIndex - Create a new jump table. /// unsigned createJumpTableIndex(const std::vector &DestBBs); - + /// isEmpty - Return true if there are no jump tables. /// bool isEmpty() const { return JumpTables.empty(); } @@ -105,7 +105,7 @@ public: void RemoveJumpTable(unsigned Idx) { JumpTables[Idx].MBBs.clear(); } - + /// ReplaceMBBInJumpTables - If Old is the target of any jump tables, update /// the jump tables to branch to New instead. bool ReplaceMBBInJumpTables(MachineBasicBlock *Old, MachineBasicBlock *New); -- cgit v1.1 From d4347e1af9141ec9f8e3e527367bfd16c0cc4ffb Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 11 May 2012 00:19:32 +0000 Subject: Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), but it generates int3 on x86 instead of ud2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ISDOpcodes.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index ab8ab5d..e570e12 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -582,6 +582,9 @@ namespace ISD { // TRAP - Trapping instruction TRAP, + // DEBUGGER - Trap intented to get the attention of a debugger. + DEBUGGER, + // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are // their first operand. The other operands are the address to prefetch, // read / write specifier, locality specifier and instruction / data cache -- cgit v1.1 From a6063c6e29746d9425bdf46d680e28a48dcf58f9 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 14 May 2012 18:58:10 +0000 Subject: Rename @llvm.debugger to @llvm.debugtrap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ISDOpcodes.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index e570e12..7c2864f 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -582,8 +582,8 @@ namespace ISD { // TRAP - Trapping instruction TRAP, - // DEBUGGER - Trap intented to get the attention of a debugger. - DEBUGGER, + // DEBUGTRAP - Trap intented to get the attention of a debugger. + DEBUGTRAP, // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are // their first operand. The other operands are the address to prefetch, -- cgit v1.1 From c696c8bd35a8ab293879e821142dd9136201f16e Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 18 May 2012 22:10:15 +0000 Subject: Modernize naming convention for class members. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157079 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveRangeEdit.h | 50 ++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveRangeEdit.h b/include/llvm/CodeGen/LiveRangeEdit.h index 57a6193..1831a07 100644 --- a/include/llvm/CodeGen/LiveRangeEdit.h +++ b/include/llvm/CodeGen/LiveRangeEdit.h @@ -55,29 +55,29 @@ public: }; private: - LiveInterval &parent_; - SmallVectorImpl &newRegs_; + LiveInterval &Parent; + SmallVectorImpl &NewRegs; MachineRegisterInfo &MRI; LiveIntervals &LIS; VirtRegMap *VRM; const TargetInstrInfo &TII; - Delegate *const delegate_; + Delegate *const TheDelegate; - /// firstNew_ - Index of the first register added to newRegs_. - const unsigned firstNew_; + /// FirstNew - Index of the first register added to NewRegs. + const unsigned FirstNew; - /// scannedRemattable_ - true when remattable values have been identified. - bool scannedRemattable_; + /// ScannedRemattable - true when remattable values have been identified. + bool ScannedRemattable; - /// remattable_ - Values defined by remattable instructions as identified by + /// Remattable - Values defined by remattable instructions as identified by /// tii.isTriviallyReMaterializable(). - SmallPtrSet remattable_; + SmallPtrSet Remattable; - /// rematted_ - Values that were actually rematted, and so need to have their + /// Rematted - Values that were actually rematted, and so need to have their /// live range trimmed or entirely removed. - SmallPtrSet rematted_; + SmallPtrSet Rematted; - /// scanRemattable - Identify the parent_ values that may rematerialize. + /// scanRemattable - Identify the Parent values that may rematerialize. void scanRemattable(AliasAnalysis *aa); /// allUsesAvailableAt - Return true if all registers used by OrigMI at @@ -105,26 +105,26 @@ public: LiveIntervals &lis, VirtRegMap *vrm, Delegate *delegate = 0) - : parent_(parent), newRegs_(newRegs), + : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis), VRM(vrm), TII(*MF.getTarget().getInstrInfo()), - delegate_(delegate), - firstNew_(newRegs.size()), - scannedRemattable_(false) {} + TheDelegate(delegate), + FirstNew(newRegs.size()), + ScannedRemattable(false) {} - LiveInterval &getParent() const { return parent_; } - unsigned getReg() const { return parent_.reg; } + LiveInterval &getParent() const { return Parent; } + unsigned getReg() const { return Parent.reg; } /// Iterator for accessing the new registers added by this edit. typedef SmallVectorImpl::const_iterator iterator; - iterator begin() const { return newRegs_.begin()+firstNew_; } - iterator end() const { return newRegs_.end(); } - unsigned size() const { return newRegs_.size()-firstNew_; } + iterator begin() const { return NewRegs.begin()+FirstNew; } + iterator end() const { return NewRegs.end(); } + unsigned size() const { return NewRegs.size()-FirstNew; } bool empty() const { return size() == 0; } - LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; } + LiveInterval *get(unsigned idx) const { return NewRegs[idx+FirstNew]; } ArrayRef regs() const { - return makeArrayRef(newRegs_).slice(firstNew_); + return makeArrayRef(NewRegs).slice(FirstNew); } /// createFrom - Create a new virtual register based on OldReg. @@ -174,12 +174,12 @@ public: /// markRematerialized - explicitly mark a value as rematerialized after doing /// it manually. void markRematerialized(const VNInfo *ParentVNI) { - rematted_.insert(ParentVNI); + Rematted.insert(ParentVNI); } /// didRematerialize - Return true if ParentVNI was rematerialized anywhere. bool didRematerialize(const VNInfo *ParentVNI) const { - return rematted_.count(ParentVNI); + return Rematted.count(ParentVNI); } /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try -- cgit v1.1 From 20942dcd8634ad75091fe89669868cfebf74e869 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sat, 19 May 2012 05:25:46 +0000 Subject: Allow LiveRangeEdit to be created with a NULL parent. The dead code elimination with callbacks is still useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157100 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveRangeEdit.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveRangeEdit.h b/include/llvm/CodeGen/LiveRangeEdit.h index 1831a07..def7b00 100644 --- a/include/llvm/CodeGen/LiveRangeEdit.h +++ b/include/llvm/CodeGen/LiveRangeEdit.h @@ -55,7 +55,7 @@ public: }; private: - LiveInterval &Parent; + LiveInterval *Parent; SmallVectorImpl &NewRegs; MachineRegisterInfo &MRI; LiveIntervals &LIS; @@ -99,7 +99,7 @@ public: /// @param vrm Map of virtual registers to physical registers for this /// function. If NULL, no virtual register map updates will /// be done. This could be the case if called before Regalloc. - LiveRangeEdit(LiveInterval &parent, + LiveRangeEdit(LiveInterval *parent, SmallVectorImpl &newRegs, MachineFunction &MF, LiveIntervals &lis, @@ -112,8 +112,11 @@ public: FirstNew(newRegs.size()), ScannedRemattable(false) {} - LiveInterval &getParent() const { return Parent; } - unsigned getReg() const { return Parent.reg; } + LiveInterval &getParent() const { + assert(Parent && "No parent LiveInterval"); + return *Parent; + } + unsigned getReg() const { return getParent().reg; } /// Iterator for accessing the new registers added by this edit. typedef SmallVectorImpl::const_iterator iterator; -- cgit v1.1 From c313c6b9fffa58e88c166e50a759d689686f17f0 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Sun, 20 May 2012 02:44:30 +0000 Subject: Add a LiveRangeQuery class. This class is meant to be the primary interface for examining a live range in the vicinity on a given instruction. It avoids all the messy dealings with iterators and early clobbers. This is a more abstract interface to live ranges, hiding the implementation as a vector of segments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157141 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 85 +++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 3170952..96680e5 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -500,6 +500,91 @@ namespace llvm { return OS; } + /// LiveRangeQuery - Query information about a live range around a given + /// instruction. This class hides the implementation details of live ranges, + /// and it should be used as the primary interface for examining live ranges + /// around instructions. + /// + class LiveRangeQuery { + VNInfo *EarlyVal; + VNInfo *LateVal; + SlotIndex EndPoint; + bool Kill; + + public: + /// Create a LiveRangeQuery for the given live range and instruction index. + /// The sub-instruction slot of Idx doesn't matter, only the instruction it + /// refers to is considered. + LiveRangeQuery(const LiveInterval &LI, SlotIndex Idx) + : EarlyVal(0), LateVal(0), Kill(false) { + // Find the segment that enters the instruction. + LiveInterval::const_iterator I = LI.find(Idx.getBaseIndex()); + LiveInterval::const_iterator E = LI.end(); + if (I == E) + return; + // Is this an instruction live-in segment? + if (SlotIndex::isEarlierInstr(I->start, Idx)) { + EarlyVal = I->valno; + EndPoint = I->end; + // Move to the potentially live-out segment. + if (SlotIndex::isSameInstr(Idx, I->end)) { + Kill = true; + if (++I == E) + return; + } + } + // I now points to the segment that may be live-through, or defined by + // this instr. Ignore segments starting after the current instr. + if (SlotIndex::isEarlierInstr(Idx, I->start)) + return; + LateVal = I->valno; + EndPoint = I->end; + } + + /// Return the value that is live-in to the instruction. This is the value + /// that will be read by the instruction's use operands. Return NULL if no + /// value is live-in. + VNInfo *valueIn() const { + return EarlyVal; + } + + /// Return true if the live-in value is killed by this instruction. This + /// means that either the live range ends at the instruction, or it changes + /// value. + bool isKill() const { + return Kill; + } + + /// Return true if this instruction has a dead def. + bool isDeadDef() const { + return EndPoint.isDead(); + } + + /// Return the value leaving the instruction, if any. This can be a + /// live-through value, or a live def. A dead def returns NULL. + VNInfo *valueOut() const { + return isDeadDef() ? 0 : LateVal; + } + + /// Return the value defined by this instruction, if any. This includes + /// dead defs, it is the value created by the instruction's def operands. + VNInfo *valueDefined() const { + return EarlyVal == LateVal ? 0 : LateVal; + } + + /// Return the end point of the last live range segment to interact with + /// the instruction, if any. + /// + /// The end point is an invalid SlotIndex only if the live range doesn't + /// intersect the instruction at all. + /// + /// The end point may be at or past the end of the instruction's basic + /// block. That means the value was live out of the block. + SlotIndex endPoint() const { + return EndPoint; + } + }; + /// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a /// LiveInterval into equivalence clases of connected components. A /// LiveInterval that has multiple connected components can be broken into -- cgit v1.1 From 1dc12aa148f0ecb4135fa3e47e7a2ac81ceac394 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 21 May 2012 03:11:23 +0000 Subject: Give a small negative bias to giant edge bundles. This helps compile time when the greedy register allocator splits live ranges in giant functions. Without the bias, we would try to grow regions through the giant edge bundles, usually to find out that the region became too big and expensive. If a live range has many uses in blocks near the giant bundle, the small negative bias doesn't make a big difference, and we still consider regions including the giant edge bundle. Giant edge bundles are usually connected to landing pads or indirect branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157174 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/EdgeBundles.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/EdgeBundles.h b/include/llvm/CodeGen/EdgeBundles.h index a1d29b1..e8a4a2d 100644 --- a/include/llvm/CodeGen/EdgeBundles.h +++ b/include/llvm/CodeGen/EdgeBundles.h @@ -46,7 +46,7 @@ public: unsigned getNumBundles() const { return EC.getNumClasses(); } /// getBlocks - Return an array of blocks that are connected to Bundle. - ArrayRef getBlocks(unsigned Bundle) { return Blocks[Bundle]; } + ArrayRef getBlocks(unsigned Bundle) const { return Blocks[Bundle]; } /// getMachineFunction - Return the last machine function computed. const MachineFunction *getMachineFunction() const { return MF; } -- cgit v1.1 From 0a39d4e4c86540d7c89f6dbe511b70466e132715 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Thu, 24 May 2012 22:11:09 +0000 Subject: misched: Added ScoreboardHazardRecognizer. The Hazard checker implements in-order contraints, or interlocked resources. Ready instructions with hazards do not enter the available queue and are not visible to other heuristics. The major code change is the addition of SchedBoundary to encapsulate the state at the top or bottom of the schedule, including both a pending and available queue. The scheduler now counts cycles in sync with the hazard checker. These are minimum cycle counts based on known hazards. Targets with no itinerary (x86_64) currently remain at cycle 0. To fix this, we need to provide some maximum issue width for all targets. We also need to add the concept of expected latency vs. minimum latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157427 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleHazardRecognizer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ScheduleHazardRecognizer.h b/include/llvm/CodeGen/ScheduleHazardRecognizer.h index 2f53baa..fd62841 100644 --- a/include/llvm/CodeGen/ScheduleHazardRecognizer.h +++ b/include/llvm/CodeGen/ScheduleHazardRecognizer.h @@ -55,7 +55,7 @@ public: /// other instruction is available, issue it first. /// * NoopHazard: issuing this instruction would break the program. If /// some other instruction can be issued, do so, otherwise issue a noop. - virtual HazardType getHazardType(SUnit *m, int Stalls) { + virtual HazardType getHazardType(SUnit *m, int Stalls = 0) { return NoHazard; } -- cgit v1.1 From 6e1b8128505711276a87e96f6bffb818b435cbd5 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Wed, 30 May 2012 00:17:12 +0000 Subject: Add an insertPass API to TargetPassConfig. Besides adding the new insertPass function, this patch uses it to enhance the existing -print-machineinstrs so that the MachineInstrs after a specific pass can be printed. Patch by Bin Zeng! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157655 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index e76fe99..567a9f7 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -101,6 +101,9 @@ public: /// point where StadardID is expected, add TargetID in its place. void substitutePass(char &StandardID, char &TargetID); + /// Insert InsertedPassID pass after TargetPassID pass. + void insertPass(const char &TargetPassID, const char &InsertedPassID); + /// Allow the target to enable a specific standard pass by default. void enablePass(char &ID) { substitutePass(ID, ID); } @@ -342,6 +345,9 @@ namespace llvm { /// branches. extern char &BranchFolderPassID; + /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. + extern char &MachineFunctionPrinterPassID; + /// TailDuplicate - Duplicate blocks with unconditional branches /// into tails of their predecessors. extern char &TailDuplicateID; -- cgit v1.1 From 68f25571e759c1fcf2da206109647259f49f7416 Mon Sep 17 00:00:00 2001 From: Manman Ren Date: Fri, 1 Jun 2012 19:33:18 +0000 Subject: ARM: properly handle alignment for struct byval. Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157830 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/FastISel.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index e57c8b1..9fe743e 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -299,6 +299,15 @@ protected: unsigned Op1, bool Op1IsKill, uint64_t Imm); + /// FastEmitInst_rrii - Emit a MachineInstr with two register operands, + /// two immediates operands, and a result register in the given register + /// class. + unsigned FastEmitInst_rrii(unsigned MachineInstOpcode, + const TargetRegisterClass *RC, + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm1, uint64_t Imm2); + /// FastEmitInst_i - Emit a MachineInstr with a single immediate /// operand, and a result register in the given register class. unsigned FastEmitInst_i(unsigned MachineInstrOpcode, -- cgit v1.1 From 396618b43a85e12d290a90b181c6af5d7c0c5f11 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 1 Jun 2012 23:28:30 +0000 Subject: Switch all register list clients to the new MC*Iterator interface. No functional change intended. Sorry for the churn. The iterator classes are supposed to help avoid giant commits like this one in the future. The TableGen-produced register lists are getting quite large, and it may be necessary to change the table representation. This makes it possible to do so without changing all clients (again). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineRegisterInfo.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h index 3272fbd..5a82caa 100644 --- a/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/include/llvm/CodeGen/MachineRegisterInfo.h @@ -336,7 +336,7 @@ public: bool isPhysRegOrOverlapUsed(unsigned Reg) const { if (UsedPhysRegMask.test(Reg)) return true; - for (const uint16_t *AI = TRI->getOverlaps(Reg); *AI; ++AI) + for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) if (UsedPhysRegs.test(*AI)) return true; return false; -- cgit v1.1 From d9b0b025612992a0b724eeca8bdf10b1d7a5c355 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 2 Jun 2012 10:20:22 +0000 Subject: Fix typos found by http://github.com/lyda/misspell-check git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ISDOpcodes.h | 2 +- include/llvm/CodeGen/ScheduleDAGInstrs.h | 2 +- include/llvm/CodeGen/SlotIndexes.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index 7c2864f..e380650 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -582,7 +582,7 @@ namespace ISD { // TRAP - Trapping instruction TRAP, - // DEBUGTRAP - Trap intented to get the attention of a debugger. + // DEBUGTRAP - Trap intended to get the attention of a debugger. DEBUGTRAP, // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index dcf72c7..968cc56 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -230,7 +230,7 @@ namespace llvm { /// LoopDependencies LoopRegs; - /// DbgValues - Remember instruction that preceeds DBG_VALUE. + /// DbgValues - Remember instruction that precedes DBG_VALUE. /// These are generated by buildSchedGraph but persist so they can be /// referenced when emitting the final schedule. typedef std::vector > diff --git a/include/llvm/CodeGen/SlotIndexes.h b/include/llvm/CodeGen/SlotIndexes.h index 02d64c9..c7fa512 100644 --- a/include/llvm/CodeGen/SlotIndexes.h +++ b/include/llvm/CodeGen/SlotIndexes.h @@ -576,7 +576,7 @@ namespace llvm { nextItr = getIndexAfter(mi).listEntry(); prevItr = prior(nextItr); } else { - // Insert mi's index immediately after the preceeding instruction. + // Insert mi's index immediately after the preceding instruction. prevItr = getIndexBefore(mi).listEntry(); nextItr = llvm::next(prevItr); } -- cgit v1.1 From 15f1d8c557c217b90a82599d5f0f849f8340a1e3 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 4 Jun 2012 22:39:14 +0000 Subject: Switch LiveIntervals member variable to LLVM naming standards. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157957 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 82 ++++++++++++++--------------- 1 file changed, 41 insertions(+), 41 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 3cc31ad..edf80f5 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -44,27 +44,27 @@ namespace llvm { class VirtRegMap; class LiveIntervals : public MachineFunctionPass { - MachineFunction* mf_; - MachineRegisterInfo* mri_; - const TargetMachine* tm_; - const TargetRegisterInfo* tri_; - const TargetInstrInfo* tii_; - AliasAnalysis *aa_; - LiveVariables* lv_; - SlotIndexes* indexes_; + MachineFunction* MF; + MachineRegisterInfo* MRI; + const TargetMachine* TM; + const TargetRegisterInfo* TRI; + const TargetInstrInfo* TII; + AliasAnalysis *AA; + LiveVariables* LV; + SlotIndexes* Indexes; /// Special pool allocator for VNInfo's (LiveInterval val#). /// VNInfo::Allocator VNInfoAllocator; typedef DenseMap Reg2IntervalMap; - Reg2IntervalMap r2iMap_; + Reg2IntervalMap R2IMap; - /// allocatableRegs_ - A bit vector of allocatable registers. - BitVector allocatableRegs_; + /// AllocatableRegs - A bit vector of allocatable registers. + BitVector AllocatableRegs; - /// reservedRegs_ - A bit vector of reserved registers. - BitVector reservedRegs_; + /// ReservedRegs - A bit vector of reserved registers. + BitVector ReservedRegs; /// RegMaskSlots - Sorted list of instructions with register mask operands. /// Always use the 'r' slot, RegMasks are normal clobbers, not early @@ -103,38 +103,38 @@ namespace llvm { typedef Reg2IntervalMap::iterator iterator; typedef Reg2IntervalMap::const_iterator const_iterator; - const_iterator begin() const { return r2iMap_.begin(); } - const_iterator end() const { return r2iMap_.end(); } - iterator begin() { return r2iMap_.begin(); } - iterator end() { return r2iMap_.end(); } - unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); } + const_iterator begin() const { return R2IMap.begin(); } + const_iterator end() const { return R2IMap.end(); } + iterator begin() { return R2IMap.begin(); } + iterator end() { return R2IMap.end(); } + unsigned getNumIntervals() const { return (unsigned)R2IMap.size(); } LiveInterval &getInterval(unsigned reg) { - Reg2IntervalMap::iterator I = r2iMap_.find(reg); - assert(I != r2iMap_.end() && "Interval does not exist for register"); + Reg2IntervalMap::iterator I = R2IMap.find(reg); + assert(I != R2IMap.end() && "Interval does not exist for register"); return *I->second; } const LiveInterval &getInterval(unsigned reg) const { - Reg2IntervalMap::const_iterator I = r2iMap_.find(reg); - assert(I != r2iMap_.end() && "Interval does not exist for register"); + Reg2IntervalMap::const_iterator I = R2IMap.find(reg); + assert(I != R2IMap.end() && "Interval does not exist for register"); return *I->second; } bool hasInterval(unsigned reg) const { - return r2iMap_.count(reg); + return R2IMap.count(reg); } /// isAllocatable - is the physical register reg allocatable in the current /// function? bool isAllocatable(unsigned reg) const { - return allocatableRegs_.test(reg); + return AllocatableRegs.test(reg); } /// isReserved - is the physical register reg reserved in the current /// function bool isReserved(unsigned reg) const { - return reservedRegs_.test(reg); + return ReservedRegs.test(reg); } /// getApproximateInstructionCount - computes an estimate of the number @@ -145,9 +145,9 @@ namespace llvm { // Interval creation LiveInterval &getOrCreateInterval(unsigned reg) { - Reg2IntervalMap::iterator I = r2iMap_.find(reg); - if (I == r2iMap_.end()) - I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first; + Reg2IntervalMap::iterator I = R2IMap.find(reg); + if (I == R2IMap.end()) + I = R2IMap.insert(std::make_pair(reg, createInterval(reg))).first; return *I->second; } @@ -173,39 +173,39 @@ namespace llvm { // Interval removal void removeInterval(unsigned Reg) { - DenseMap::iterator I = r2iMap_.find(Reg); + DenseMap::iterator I = R2IMap.find(Reg); delete I->second; - r2iMap_.erase(I); + R2IMap.erase(I); } SlotIndexes *getSlotIndexes() const { - return indexes_; + return Indexes; } /// isNotInMIMap - returns true if the specified machine instr has been /// removed or was never entered in the map. bool isNotInMIMap(const MachineInstr* Instr) const { - return !indexes_->hasIndex(Instr); + return !Indexes->hasIndex(Instr); } /// Returns the base index of the given instruction. SlotIndex getInstructionIndex(const MachineInstr *instr) const { - return indexes_->getInstructionIndex(instr); + return Indexes->getInstructionIndex(instr); } /// Returns the instruction associated with the given index. MachineInstr* getInstructionFromIndex(SlotIndex index) const { - return indexes_->getInstructionFromIndex(index); + return Indexes->getInstructionFromIndex(index); } /// Return the first index in the given basic block. SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const { - return indexes_->getMBBStartIdx(mbb); + return Indexes->getMBBStartIdx(mbb); } /// Return the last index in the given basic block. SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const { - return indexes_->getMBBEndIdx(mbb); + return Indexes->getMBBEndIdx(mbb); } bool isLiveInToMBB(const LiveInterval &li, @@ -219,24 +219,24 @@ namespace llvm { } MachineBasicBlock* getMBBFromIndex(SlotIndex index) const { - return indexes_->getMBBFromIndex(index); + return Indexes->getMBBFromIndex(index); } SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) { - return indexes_->insertMachineInstrInMaps(MI); + return Indexes->insertMachineInstrInMaps(MI); } void RemoveMachineInstrFromMaps(MachineInstr *MI) { - indexes_->removeMachineInstrFromMaps(MI); + Indexes->removeMachineInstrFromMaps(MI); } void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) { - indexes_->replaceMachineInstrInMaps(MI, NewMI); + Indexes->replaceMachineInstrInMaps(MI, NewMI); } bool findLiveInMBBs(SlotIndex Start, SlotIndex End, SmallVectorImpl &MBBs) const { - return indexes_->findLiveInMBBs(Start, End, MBBs); + return Indexes->findLiveInMBBs(Start, End, MBBs); } VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; } -- cgit v1.1 From 84423c8778ed22877c123fe41f5e137cb5a30e90 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 4 Jun 2012 23:01:41 +0000 Subject: Delete dead code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157963 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index edf80f5..39df32c 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -151,10 +151,6 @@ namespace llvm { return *I->second; } - /// dupInterval - Duplicate a live interval. The caller is responsible for - /// managing the allocated memory. - LiveInterval *dupInterval(LiveInterval *li); - /// addLiveRangeToEndOfBlock - Given a register and an instruction, /// adds a live range from that instruction to the end of its MBB. LiveRange addLiveRangeToEndOfBlock(unsigned reg, -- cgit v1.1 From 3dfd59bdc3ab1135961a3798b4f23e191a7dc953 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 5 Jun 2012 01:06:12 +0000 Subject: Stop using LiveIntervals::isReMaterializable(). It is an old function that does a lot more than required by CalcSpillWeights, which was the only remaining caller. The isRematerializable() function never actually sets the isLoad argument, so don't try to compute that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157973 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 39df32c..ba5ab3e 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -178,6 +178,10 @@ namespace llvm { return Indexes; } + AliasAnalysis *getAliasAnalysis() const { + return AA; + } + /// isNotInMIMap - returns true if the specified machine instr has been /// removed or was never entered in the map. bool isNotInMIMap(const MachineInstr* Instr) const { -- cgit v1.1 From afb32f7fb482d62532d575ea7b1ee8ab3919575c Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 5 Jun 2012 01:06:15 +0000 Subject: Remove the last remat-related code from LiveIntervalAnalysis. Rematerialization is handled by LiveRangeEdit now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157974 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index ba5ab3e..5ed5426 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -361,26 +361,6 @@ namespace llvm { SlotIndex MIIdx, LiveInterval &interval); - /// getReMatImplicitUse - If the remat definition MI has one (for now, we - /// only allow one) virtual register operand, then its uses are implicitly - /// using the register. Returns the virtual register. - unsigned getReMatImplicitUse(const LiveInterval &li, - MachineInstr *MI) const; - - /// isValNoAvailableAt - Return true if the val# of the specified interval - /// which reaches the given instruction also reaches the specified use - /// index. - bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI, - SlotIndex UseIdx) const; - - /// isReMaterializable - Returns true if the definition MI of the specified - /// val# of the specified interval is re-materializable. Also returns true - /// by reference if the def is a load. - bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo, - MachineInstr *MI, - const SmallVectorImpl *SpillIs, - bool &isLoad); - static LiveInterval* createInterval(unsigned Reg); void printInstrs(raw_ostream &O) const; -- cgit v1.1 From d327d3ddddaf23fe920a01bf6304f6a8f4986e89 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Tue, 5 Jun 2012 03:44:32 +0000 Subject: misched: Allow disabling scoreboard hazard checking for subtargets with a valid itinerary but no pipeline stages. An itinerary can contain useful scheduling information without specifying pipeline stages for each instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157977 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleHazardRecognizer.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ScheduleHazardRecognizer.h b/include/llvm/CodeGen/ScheduleHazardRecognizer.h index fd62841..9dfa344 100644 --- a/include/llvm/CodeGen/ScheduleHazardRecognizer.h +++ b/include/llvm/CodeGen/ScheduleHazardRecognizer.h @@ -46,6 +46,8 @@ public: /// atIssueLimit - Return true if no more instructions may be issued in this /// cycle. + /// + /// FIXME: remove this once MachineScheduler is the only client. virtual bool atIssueLimit() const { return false; } /// getHazardType - Return the hazard type of emitting this node. There are -- cgit v1.1 From 9a314da5812dc14bb37df47b89041f8059efc8b1 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 5 Jun 2012 17:19:07 +0000 Subject: Remove dead function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158005 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 5ed5426..76f12eb 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -137,12 +137,6 @@ namespace llvm { return ReservedRegs.test(reg); } - /// getApproximateInstructionCount - computes an estimate of the number - /// of instructions in a given LiveInterval. - unsigned getApproximateInstructionCount(LiveInterval& I) { - return I.getSize()/SlotIndex::InstrDist; - } - // Interval creation LiveInterval &getOrCreateInterval(unsigned reg) { Reg2IntervalMap::iterator I = R2IMap.find(reg); -- cgit v1.1 From b7e0289fb320c8440ba5eed121a8b932dbd806a2 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Tue, 5 Jun 2012 21:11:27 +0000 Subject: misched: API for minimum vs. expected latency. Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158021 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAG.h | 15 ++++++--------- include/llvm/CodeGen/ScheduleDAGInstrs.h | 10 +++++++--- 2 files changed, 13 insertions(+), 12 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index f4de693..3dd3c0c 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -272,6 +272,9 @@ namespace llvm { unsigned Depth; // Node depth. unsigned Height; // Node height. public: + unsigned TopReadyCycle; // Cycle relative to start when node is ready. + unsigned BotReadyCycle; // Cycle relative to end when node is ready. + const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. const TargetRegisterClass *CopySrcRC; @@ -287,7 +290,7 @@ namespace llvm { isScheduleHigh(false), isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), - CopyDstRC(NULL), CopySrcRC(NULL) {} + TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {} /// SUnit - Construct an SUnit for post-regalloc scheduling to represent /// a MachineInstr. @@ -301,7 +304,7 @@ namespace llvm { isScheduleHigh(false), isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), - CopyDstRC(NULL), CopySrcRC(NULL) {} + TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {} /// SUnit - Construct a placeholder SUnit. SUnit() @@ -314,7 +317,7 @@ namespace llvm { isScheduleHigh(false), isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), - CopyDstRC(NULL), CopySrcRC(NULL) {} + TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {} /// setNode - Assign the representative SDNode for this SUnit. /// This may be used during pre-regalloc scheduling. @@ -552,12 +555,6 @@ namespace llvm { /// virtual void computeLatency(SUnit *SU) = 0; - /// ComputeOperandLatency - Override dependence edge latency using - /// operand use/def information - /// - virtual void computeOperandLatency(SUnit *, SUnit *, - SDep&) const { } - /// ForceUnitLatencies - Return true if all scheduling edges should be given /// a latency value of one. The default is to return false; schedulers may /// override this as needed. diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index 968cc56..874f9f1 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -291,11 +291,15 @@ namespace llvm { /// virtual void computeLatency(SUnit *SU); - /// computeOperandLatency - Override dependence edge latency using + /// computeOperandLatency - Return dependence edge latency using /// operand use/def information /// - virtual void computeOperandLatency(SUnit *Def, SUnit *Use, - SDep& dep) const; + /// FindMin may be set to get the minimum vs. expected latency. Minimum + /// latency is used for scheduling groups, while expected latency is for + /// instruction cost and critical path. + virtual unsigned computeOperandLatency(SUnit *Def, SUnit *Use, + const SDep& dep, + bool FindMin = false) const; /// schedule - Order nodes according to selected style, filling /// in the Sequence member. -- cgit v1.1 From 4e53a40ea321c43bdf754147dd2ec064985e5b7b Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 5 Jun 2012 21:54:09 +0000 Subject: Implement LiveRangeCalc::extendToUses() and createDeadDefs(). These LiveRangeCalc methods are to be used when computing a live range from scratch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158027 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 96680e5..1016391 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -274,6 +274,11 @@ namespace llvm { return VNI; } + /// createDeadDef - Make sure the interval has a value defined at Def. + /// If one already exists, return it. Otherwise allocate a new value and + /// add liveness for a dead def. + VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator); + /// Create a copy of the given value. The new value will be identical except /// for the Value number. VNInfo *createValueCopy(const VNInfo *orig, -- cgit v1.1 From 34c6f9803499c11ed2dc8479ec768d47370a2d3a Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 5 Jun 2012 22:02:15 +0000 Subject: Add experimental support for register unit liveness. Instead of computing a live interval per physreg, LiveIntervals can compute live intervals per register unit. This makes impossible the confusing situation where aliasing registers could have overlapping live intervals. It should also make fixed interferernce checking cheaper since registers have fewer register units than aliases. Live intervals for regunits are computed on demand, using MRI use-def chains and the new LiveRangeCalc class. Only regunits live in to ABI blocks are precomputed during LiveIntervals::runOnMachineFunction(). The regunit liveness computations don't depend on LiveVariables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158029 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 44 +++++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 76f12eb..bd3604c 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -35,7 +35,9 @@ namespace llvm { class AliasAnalysis; + class LiveRangeCalc; class LiveVariables; + class MachineDominatorTree; class MachineLoopInfo; class TargetRegisterInfo; class MachineRegisterInfo; @@ -52,6 +54,8 @@ namespace llvm { AliasAnalysis *AA; LiveVariables* LV; SlotIndexes* Indexes; + MachineDominatorTree *DomTree; + LiveRangeCalc *LRCalc; /// Special pool allocator for VNInfo's (LiveInterval val#). /// @@ -92,11 +96,14 @@ namespace llvm { /// block. SmallVector, 8> RegMaskBlocks; + /// RegUnitIntervals - Keep a live interval for each register unit as a way + /// of tracking fixed physreg interference. + SmallVector RegUnitIntervals; + public: static char ID; // Pass identification, replacement for typeid - LiveIntervals() : MachineFunctionPass(ID) { - initializeLiveIntervalsPass(*PassRegistry::getPassRegistry()); - } + LiveIntervals(); + virtual ~LiveIntervals(); // Calculate the spill weight to assign to a single instruction. static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth); @@ -317,6 +324,34 @@ namespace llvm { bool checkRegMaskInterference(LiveInterval &LI, BitVector &UsableRegs); + // Register unit functions. + // + // Fixed interference occurs when MachineInstrs use physregs directly + // instead of virtual registers. This typically happens when passing + // arguments to a function call, or when instructions require operands in + // fixed registers. + // + // Each physreg has one or more register units, see MCRegisterInfo. We + // track liveness per register unit to handle aliasing registers more + // efficiently. + + /// getRegUnit - Return the live range for Unit. + /// It will be computed if it doesn't exist. + LiveInterval &getRegUnit(unsigned Unit) { + LiveInterval *LI = RegUnitIntervals[Unit]; + if (!LI) { + // Compute missing ranges on demand. + RegUnitIntervals[Unit] = LI = new LiveInterval(Unit, HUGE_VALF); + computeRegUnitInterval(LI); + } + return *LI; + } + + /// trackingRegUnits - Does LiveIntervals curently track register units? + /// This function will be removed when regunit tracking is permanently + /// enabled. + bool trackingRegUnits() const { return !RegUnitIntervals.empty(); } + private: /// computeIntervals - Compute live intervals. void computeIntervals(); @@ -360,6 +395,9 @@ namespace llvm { void printInstrs(raw_ostream &O) const; void dumpInstrs() const; + void computeLiveInRegUnits(); + void computeRegUnitInterval(LiveInterval*); + class HMEditor; }; } // End llvm namespace -- cgit v1.1 From b77ec7d26405125fa5685370af5f17fcc9edbecd Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 5 Jun 2012 22:51:54 +0000 Subject: Simplify LiveInterval::print(). Don't print out the register number and spill weight, making the TRI argument unnecessary. This allows callers to interpret the reg field. It can currently be a virtual register, a physical register, a spill slot, or a register unit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158031 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 1016391..30acaff 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -486,7 +486,7 @@ namespace llvm { (thisIndex == otherIndex && reg < other.reg)); } - void print(raw_ostream &OS, const TargetRegisterInfo *TRI = 0) const; + void print(raw_ostream &OS) const; void dump() const; private: -- cgit v1.1 From a7542d5f870c5d98960d1676e23ac1d1d975d7e5 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Wed, 6 Jun 2012 18:25:08 +0000 Subject: Remove unused private fields found by clang's new -Wunused-private-field. There are some that I didn't remove this round because they looked like obvious stubs. There are dead variables in gtest too, they should be fixed upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158090 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAGInstrs.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index 874f9f1..1bde942 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -36,7 +36,6 @@ namespace llvm { /// scheduled as soon as possible after the variable's last use. /// class LoopDependencies { - const MachineLoopInfo &MLI; const MachineDominatorTree &MDT; public: @@ -44,9 +43,7 @@ namespace llvm { LoopDeps; LoopDeps Deps; - LoopDependencies(const MachineLoopInfo &mli, - const MachineDominatorTree &mdt) : - MLI(mli), MDT(mdt) {} + LoopDependencies(const MachineDominatorTree &mdt) : MDT(mdt) {} /// VisitLoop - Clear out any previous state and analyze the given loop. /// -- cgit v1.1 From afc2657cc33988a178d3b21645dba54484600c5f Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 6 Jun 2012 19:47:35 +0000 Subject: Move RegisterPressure.h. Make it a general utility for use by Targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158097 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/RegisterPressure.h | 255 ++++++++++++++++++++++++++++++++ 1 file changed, 255 insertions(+) create mode 100644 include/llvm/CodeGen/RegisterPressure.h (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/RegisterPressure.h b/include/llvm/CodeGen/RegisterPressure.h new file mode 100644 index 0000000..dd7ba86 --- /dev/null +++ b/include/llvm/CodeGen/RegisterPressure.h @@ -0,0 +1,255 @@ +//===-- RegisterPressure.h - Dynamic Register Pressure -*- C++ -*-------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the RegisterPressure class which can be used to track +// MachineInstr level register pressure. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H +#define LLVM_CODEGEN_REGISTERPRESSURE_H + +#include "llvm/CodeGen/SlotIndexes.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/ADT/SparseSet.h" + +namespace llvm { + +class LiveIntervals; +class RegisterClassInfo; +class MachineInstr; + +/// Base class for register pressure results. +struct RegisterPressure { + /// Map of max reg pressure indexed by pressure set ID, not class ID. + std::vector MaxSetPressure; + + /// List of live in registers. + SmallVector LiveInRegs; + SmallVector LiveOutRegs; + + /// Increase register pressure for each pressure set impacted by this register + /// class. Normally called by RegPressureTracker, but may be called manually + /// to account for live through (global liveness). + void increase(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI); + + /// Decrease register pressure for each pressure set impacted by this register + /// class. This is only useful to account for spilling or rematerialization. + void decrease(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI); + + void dump(const TargetRegisterInfo *TRI); +}; + +/// RegisterPressure computed within a region of instructions delimited by +/// TopIdx and BottomIdx. During pressure computation, the maximum pressure per +/// register pressure set is increased. Once pressure within a region is fully +/// computed, the live-in and live-out sets are recorded. +/// +/// This is preferable to RegionPressure when LiveIntervals are available, +/// because delimiting regions by SlotIndex is more robust and convenient than +/// holding block iterators. The block contents can change without invalidating +/// the pressure result. +struct IntervalPressure : RegisterPressure { + /// Record the boundary of the region being tracked. + SlotIndex TopIdx; + SlotIndex BottomIdx; + + void reset(); + + void openTop(SlotIndex NextTop); + + void openBottom(SlotIndex PrevBottom); +}; + +/// RegisterPressure computed within a region of instructions delimited by +/// TopPos and BottomPos. This is a less precise version of IntervalPressure for +/// use when LiveIntervals are unavailable. +struct RegionPressure : RegisterPressure { + /// Record the boundary of the region being tracked. + MachineBasicBlock::const_iterator TopPos; + MachineBasicBlock::const_iterator BottomPos; + + void reset(); + + void openTop(MachineBasicBlock::const_iterator PrevTop); + + void openBottom(MachineBasicBlock::const_iterator PrevBottom); +}; + +/// An element of pressure difference that identifies the pressure set and +/// amount of increase or decrease in units of pressure. +struct PressureElement { + unsigned PSetID; + int UnitIncrease; + + PressureElement(): PSetID(~0U), UnitIncrease(0) {} + PressureElement(unsigned id, int inc): PSetID(id), UnitIncrease(inc) {} + + bool isValid() const { return PSetID != ~0U; } +}; + +/// Store the effects of a change in pressure on things that MI scheduler cares +/// about. +/// +/// Excess records the value of the largest difference in register units beyond +/// the target's pressure limits across the affected pressure sets, where +/// largest is defined as the absolute value of the difference. Negative +/// ExcessUnits indicates a reduction in pressure that had already exceeded the +/// target's limits. +/// +/// CriticalMax records the largest increase in the tracker's max pressure that +/// exceeds the critical limit for some pressure set determined by the client. +/// +/// CurrentMax records the largest increase in the tracker's max pressure that +/// exceeds the current limit for some pressure set determined by the client. +struct RegPressureDelta { + PressureElement Excess; + PressureElement CriticalMax; + PressureElement CurrentMax; + + RegPressureDelta() {} +}; + +/// Track the current register pressure at some position in the instruction +/// stream, and remember the high water mark within the region traversed. This +/// does not automatically consider live-through ranges. The client may +/// independently adjust for global liveness. +/// +/// Each RegPressureTracker only works within a MachineBasicBlock. Pressure can +/// be tracked across a larger region by storing a RegisterPressure result at +/// each block boundary and explicitly adjusting pressure to account for block +/// live-in and live-out register sets. +/// +/// RegPressureTracker holds a reference to a RegisterPressure result that it +/// computes incrementally. During downward tracking, P.BottomIdx or P.BottomPos +/// is invalid until it reaches the end of the block or closeRegion() is +/// explicitly called. Similarly, P.TopIdx is invalid during upward +/// tracking. Changing direction has the side effect of closing region, and +/// traversing past TopIdx or BottomIdx reopens it. +class RegPressureTracker { + const MachineFunction *MF; + const TargetRegisterInfo *TRI; + const RegisterClassInfo *RCI; + const MachineRegisterInfo *MRI; + const LiveIntervals *LIS; + + /// We currently only allow pressure tracking within a block. + const MachineBasicBlock *MBB; + + /// Track the max pressure within the region traversed so far. + RegisterPressure &P; + + /// Run in two modes dependending on whether constructed with IntervalPressure + /// or RegisterPressure. If requireIntervals is false, LIS are ignored. + bool RequireIntervals; + + /// Register pressure corresponds to liveness before this instruction + /// iterator. It may point to the end of the block rather than an instruction. + MachineBasicBlock::const_iterator CurrPos; + + /// Pressure map indexed by pressure set ID, not class ID. + std::vector CurrSetPressure; + + /// List of live registers. + SparseSet LivePhysRegs; + SparseSet LiveVirtRegs; + +public: + RegPressureTracker(IntervalPressure &rp) : + MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {} + + RegPressureTracker(RegionPressure &rp) : + MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {} + + void init(const MachineFunction *mf, const RegisterClassInfo *rci, + const LiveIntervals *lis, const MachineBasicBlock *mbb, + MachineBasicBlock::const_iterator pos); + + /// Force liveness of registers. Particularly useful to initialize the + /// livein/out state of the tracker before the first call to advance/recede. + void addLiveRegs(ArrayRef Regs); + + /// Get the MI position corresponding to this register pressure. + MachineBasicBlock::const_iterator getPos() const { return CurrPos; } + + // Reset the MI position corresponding to the register pressure. This allows + // schedulers to move instructions above the RegPressureTracker's + // CurrPos. Since the pressure is computed before CurrPos, the iterator + // position changes while pressure does not. + void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; } + + /// Recede across the previous instruction. + bool recede(); + + /// Advance across the current instruction. + bool advance(); + + /// Finalize the region boundaries and recored live ins and live outs. + void closeRegion(); + + /// Get the resulting register pressure over the traversed region. + /// This result is complete if either advance() or recede() has returned true, + /// or if closeRegion() was explicitly invoked. + RegisterPressure &getPressure() { return P; } + + void discoverPhysLiveIn(unsigned Reg); + void discoverPhysLiveOut(unsigned Reg); + + void discoverVirtLiveIn(unsigned Reg); + void discoverVirtLiveOut(unsigned Reg); + + bool isTopClosed() const; + bool isBottomClosed() const; + + void closeTop(); + void closeBottom(); + + /// Consider the pressure increase caused by traversing this instruction + /// bottom-up. Find the pressure set with the most change beyond its pressure + /// limit based on the tracker's current pressure, and record the number of + /// excess register units of that pressure set introduced by this instruction. + void getMaxUpwardPressureDelta(const MachineInstr *MI, + RegPressureDelta &Delta, + ArrayRef CriticalPSets, + ArrayRef MaxPressureLimit); + + /// Consider the pressure increase caused by traversing this instruction + /// top-down. Find the pressure set with the most change beyond its pressure + /// limit based on the tracker's current pressure, and record the number of + /// excess register units of that pressure set introduced by this instruction. + void getMaxDownwardPressureDelta(const MachineInstr *MI, + RegPressureDelta &Delta, + ArrayRef CriticalPSets, + ArrayRef MaxPressureLimit); + + /// Find the pressure set with the most change beyond its pressure limit after + /// traversing this instruction either upward or downward depending on the + /// closed end of the current region. + void getMaxPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, + ArrayRef CriticalPSets, + ArrayRef MaxPressureLimit) { + if (isTopClosed()) + return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets, + MaxPressureLimit); + + assert(isBottomClosed() && "Uninitialized pressure tracker"); + return getMaxUpwardPressureDelta(MI, Delta, CriticalPSets, + MaxPressureLimit); + } + +protected: + void increasePhysRegPressure(ArrayRef Regs); + void decreasePhysRegPressure(ArrayRef Regs); + + void increaseVirtRegPressure(ArrayRef Regs); + void decreaseVirtRegPressure(ArrayRef Regs); +}; +} // end namespace llvm + +#endif -- cgit v1.1 From 1525260b3e50cc578939ef41b60609689eecfdd2 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 6 Jun 2012 20:29:31 +0000 Subject: Move RegisterClassInfo.h. Allow targets to access this API. It's required for RegisterPressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158102 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/RegisterClassInfo.h | 132 +++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 include/llvm/CodeGen/RegisterClassInfo.h (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/RegisterClassInfo.h b/include/llvm/CodeGen/RegisterClassInfo.h new file mode 100644 index 0000000..400e1f4 --- /dev/null +++ b/include/llvm/CodeGen/RegisterClassInfo.h @@ -0,0 +1,132 @@ +//===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the RegisterClassInfo class which provides dynamic +// information about target register classes. Callee saved and reserved +// registers depends on calling conventions and other dynamic information, so +// some things cannot be determined statically. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H +#define LLVM_CODEGEN_REGISTERCLASSINFO_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/OwningPtr.h" +#include "llvm/Target/TargetRegisterInfo.h" + +namespace llvm { + +class RegisterClassInfo { + struct RCInfo { + unsigned Tag; + unsigned NumRegs; + bool ProperSubClass; + OwningArrayPtr Order; + + RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {} + operator ArrayRef() const { + return makeArrayRef(Order.get(), NumRegs); + } + }; + + // Brief cached information for each register class. + OwningArrayPtr RegClass; + + // Tag changes whenever cached information needs to be recomputed. An RCInfo + // entry is valid when its tag matches. + unsigned Tag; + + const MachineFunction *MF; + const TargetRegisterInfo *TRI; + + // Callee saved registers of last MF. Assumed to be valid until the next + // runOnFunction() call. + const uint16_t *CalleeSaved; + + // Map register number to CalleeSaved index + 1; + SmallVector CSRNum; + + // Reserved registers in the current MF. + BitVector Reserved; + + // Compute all information about RC. + void compute(const TargetRegisterClass *RC) const; + + // Return an up-to-date RCInfo for RC. + const RCInfo &get(const TargetRegisterClass *RC) const { + const RCInfo &RCI = RegClass[RC->getID()]; + if (Tag != RCI.Tag) + compute(RC); + return RCI; + } + +public: + RegisterClassInfo(); + + /// runOnFunction - Prepare to answer questions about MF. This must be called + /// before any other methods are used. + void runOnMachineFunction(const MachineFunction &MF); + + /// getNumAllocatableRegs - Returns the number of actually allocatable + /// registers in RC in the current function. + unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { + return get(RC).NumRegs; + } + + /// getOrder - Returns the preferred allocation order for RC. The order + /// contains no reserved registers, and registers that alias callee saved + /// registers come last. + ArrayRef getOrder(const TargetRegisterClass *RC) const { + return get(RC); + } + + /// isProperSubClass - Returns true if RC has a legal super-class with more + /// allocatable registers. + /// + /// Register classes like GR32_NOSP are not proper sub-classes because %esp + /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb + /// mode because the GPR super-class is not legal. + bool isProperSubClass(const TargetRegisterClass *RC) const { + return get(RC).ProperSubClass; + } + + /// getLastCalleeSavedAlias - Returns the last callee saved register that + /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR. + unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { + assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); + if (unsigned N = CSRNum[PhysReg]) + return CalleeSaved[N-1]; + return 0; + } + + /// isReserved - Returns true when PhysReg is a reserved register. + /// + /// Reserved registers may belong to an allocatable register class, but the + /// target has explicitly requested that they are not used. + /// + bool isReserved(unsigned PhysReg) const { + return Reserved.test(PhysReg); + } + + /// isAllocatable - Returns true when PhysReg belongs to an allocatable + /// register class and it hasn't been reserved. + /// + /// Allocatable registers may show up in the allocation order of some virtual + /// register, so a register allocator needs to track its liveness and + /// availability. + bool isAllocatable(unsigned PhysReg) const { + return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg); + } +}; +} // end namespace llvm + +#endif + -- cgit v1.1 From 4efea94fa54d0e8687b965fdf3ba46022c8e15c4 Mon Sep 17 00:00:00 2001 From: Pete Cooper Date: Thu, 7 Jun 2012 04:43:52 +0000 Subject: Add internal read flags to MachineInstrBuilder and hook them into the MachineOperand flag of the same name git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158137 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstrBuilder.h | 7 ++++++- include/llvm/CodeGen/MachineOperand.h | 5 +++-- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index 99849a6..9192474 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -34,6 +34,7 @@ namespace RegState { Undef = 0x20, EarlyClobber = 0x40, Debug = 0x80, + InternalRead = 0x100, DefineNoRead = Define | Undef, ImplicitDefine = Implicit | Define, ImplicitKill = Implicit | Kill @@ -67,7 +68,8 @@ public: flags & RegState::Undef, flags & RegState::EarlyClobber, SubReg, - flags & RegState::Debug)); + flags & RegState::Debug, + flags & RegState::InternalRead)); return *this; } @@ -310,6 +312,9 @@ inline unsigned getDeadRegState(bool B) { inline unsigned getUndefRegState(bool B) { return B ? RegState::Undef : 0; } +inline unsigned getInternalReadRegState(bool B) { + return B ? RegState::InternalRead : 0; +} } // End llvm namespace diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index d244dd9..9ccbfe9 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -542,14 +542,15 @@ public: bool isUndef = false, bool isEarlyClobber = false, unsigned SubReg = 0, - bool isDebug = false) { + bool isDebug = false, + bool isInternalRead = false) { MachineOperand Op(MachineOperand::MO_Register); Op.IsDef = isDef; Op.IsImp = isImp; Op.IsKill = isKill; Op.IsDead = isDead; Op.IsUndef = isUndef; - Op.IsInternalRead = false; + Op.IsInternalRead = isInternalRead; Op.IsEarlyClobber = isEarlyClobber; Op.IsDebug = isDebug; Op.SmallContents.RegNo = Reg; -- cgit v1.1 From 05ec712e7f75635abbdd84dced69f4a45fe0f541 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 8 Jun 2012 23:44:45 +0000 Subject: Reintroduce VirtRegRewriter. OK, not really. We don't want to reintroduce the old rewriter hacks. This patch extracts virtual register rewriting as a separate pass that runs after the register allocator. This is possible now that CodeGen/Passes.cpp can configure the full optimizing register allocator pipeline. The rewriter pass uses register assignments in VirtRegMap to rewrite virtual registers to physical registers, and it inserts kill flags based on live intervals. These finalization steps are the same for the optimizing register allocators: RABasic, RAGreedy, and PBQP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158244 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 567a9f7..cc3b3d7 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -300,6 +300,10 @@ namespace llvm { /// basic blocks. extern char &SpillPlacementID; + /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as + /// assigned in VirtRegMap. + extern char &VirtRegRewriterID; + /// UnreachableMachineBlockElimination - This pass removes unreachable /// machine basic blocks. extern char &UnreachableMachineBlockElimID; -- cgit v1.1 From 77592fe39c404f3c48b06fae48b965058b3a5ee8 Mon Sep 17 00:00:00 2001 From: Dmitri Gribenko Date: Sat, 9 Jun 2012 00:01:45 +0000 Subject: Convert comments to proper Doxygen comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158248 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/GCMetadata.h | 16 ++++++++-------- include/llvm/CodeGen/GCStrategy.h | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/GCMetadata.h b/include/llvm/CodeGen/GCMetadata.h index 45469ed..2b6c35b 100644 --- a/include/llvm/CodeGen/GCMetadata.h +++ b/include/llvm/CodeGen/GCMetadata.h @@ -48,18 +48,18 @@ namespace llvm { /// PointKind - The type of a collector-safe point. /// enum PointKind { - Loop, //< Instr is a loop (backwards branch). - Return, //< Instr is a return instruction. - PreCall, //< Instr is a call instruction. - PostCall //< Instr is the return address of a call. + Loop, ///< Instr is a loop (backwards branch). + Return, ///< Instr is a return instruction. + PreCall, ///< Instr is a call instruction. + PostCall ///< Instr is the return address of a call. }; } /// GCPoint - Metadata for a collector-safe point in machine code. /// struct GCPoint { - GC::PointKind Kind; //< The kind of the safe point. - MCSymbol *Label; //< A label. + GC::PointKind Kind; ///< The kind of the safe point. + MCSymbol *Label; ///< A label. DebugLoc Loc; GCPoint(GC::PointKind K, MCSymbol *L, DebugLoc DL) @@ -69,8 +69,8 @@ namespace llvm { /// GCRoot - Metadata for a pointer to an object managed by the garbage /// collector. struct GCRoot { - int Num; //< Usually a frame index. - int StackOffset; //< Offset from the stack pointer. + int Num; ///< Usually a frame index. + int StackOffset; ///< Offset from the stack pointer. const Constant *Metadata;//< Metadata straight from the call to llvm.gcroot. GCRoot(int N, const Constant *MD) : Num(N), StackOffset(-1), Metadata(MD) {} diff --git a/include/llvm/CodeGen/GCStrategy.h b/include/llvm/CodeGen/GCStrategy.h index 1cbd36a..dfc26d7 100644 --- a/include/llvm/CodeGen/GCStrategy.h +++ b/include/llvm/CodeGen/GCStrategy.h @@ -65,14 +65,14 @@ namespace llvm { list_type Functions; protected: - unsigned NeededSafePoints; //< Bitmask of required safe points. - bool CustomReadBarriers; //< Default is to insert loads. - bool CustomWriteBarriers; //< Default is to insert stores. - bool CustomRoots; //< Default is to pass through to backend. - bool CustomSafePoints; //< Default is to use NeededSafePoints - // to find safe points. - bool InitRoots; //< If set, roots are nulled during lowering. - bool UsesMetadata; //< If set, backend must emit metadata tables. + unsigned NeededSafePoints; ///< Bitmask of required safe points. + bool CustomReadBarriers; ///< Default is to insert loads. + bool CustomWriteBarriers; ///< Default is to insert stores. + bool CustomRoots; ///< Default is to pass through to backend. + bool CustomSafePoints; ///< Default is to use NeededSafePoints + ///< to find safe points. + bool InitRoots; ///< If set, roots are nulled during lowering. + bool UsesMetadata; ///< If set, backend must emit metadata tables. public: GCStrategy(); -- cgit v1.1 From ba17293a8827a7e0e390b0a1d6075148a58d9edd Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Sat, 9 Jun 2012 02:16:58 +0000 Subject: Register pressure: added getPressureAfterInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158256 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/RegisterPressure.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/RegisterPressure.h b/include/llvm/CodeGen/RegisterPressure.h index dd7ba86..e810f8c 100644 --- a/include/llvm/CodeGen/RegisterPressure.h +++ b/include/llvm/CodeGen/RegisterPressure.h @@ -198,6 +198,10 @@ public: /// or if closeRegion() was explicitly invoked. RegisterPressure &getPressure() { return P; } + /// Get the register set pressure at the current position, which may be less + /// than the pressure across the traversed region. + std::vector &getRegSetPressureAtPos() { return CurrSetPressure; } + void discoverPhysLiveIn(unsigned Reg); void discoverPhysLiveOut(unsigned Reg); @@ -243,12 +247,32 @@ public: MaxPressureLimit); } + /// Get the pressure of each PSet after traversing this instruction bottom-up. + void getUpwardPressure(const MachineInstr *MI, + std::vector &PressureResult); + + /// Get the pressure of each PSet after traversing this instruction top-down. + void getDownwardPressure(const MachineInstr *MI, + std::vector &PressureResult); + + void getPressureAfterInst(const MachineInstr *MI, + std::vector &PressureResult) { + if (isTopClosed()) + return getUpwardPressure(MI, PressureResult); + + assert(isBottomClosed() && "Uninitialized pressure tracker"); + return getDownwardPressure(MI, PressureResult); + } + protected: void increasePhysRegPressure(ArrayRef Regs); void decreasePhysRegPressure(ArrayRef Regs); void increaseVirtRegPressure(ArrayRef Regs); void decreaseVirtRegPressure(ArrayRef Regs); + + void bumpUpwardPressure(const MachineInstr *MI); + void bumpDownwardPressure(const MachineInstr *MI); }; } // end namespace llvm -- cgit v1.1 From 20aedcdfa35f4b6494d4990cf6dd4459d7172c49 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Mon, 11 Jun 2012 15:11:12 +0000 Subject: Fix a problem with the reverse bundle iterators. This showed up the first time rend() was called on a bundled instruction in the Mips backend. Also avoid dereferencing end() in bundle_iterator::operator++(). We still don't have a place to put unit tests for this stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158310 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineBasicBlock.h | 68 ++++++++------------------------ 1 file changed, 16 insertions(+), 52 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineBasicBlock.h b/include/llvm/CodeGen/MachineBasicBlock.h index 18df69e..4371aa5 100644 --- a/include/llvm/CodeGen/MachineBasicBlock.h +++ b/include/llvm/CodeGen/MachineBasicBlock.h @@ -143,10 +143,7 @@ public: IterTy MII; public: - bundle_iterator(IterTy mii) : MII(mii) { - assert(!MII->isInsideBundle() && - "It's not legal to initialize bundle_iterator with a bundled MI"); - } + bundle_iterator(IterTy mii) : MII(mii) {} bundle_iterator(Ty &mi) : MII(mi) { assert(!mi.isInsideBundle() && @@ -176,29 +173,24 @@ public: // Increment and decrement operators... bundle_iterator &operator--() { // predecrement - Back up - do { - --MII; - } while (MII->isInsideBundle()); + do --MII; + while (MII->isInsideBundle()); return *this; } bundle_iterator &operator++() { // preincrement - Advance - do { - ++MII; - } while (MII->isInsideBundle()); + IterTy E = MII->getParent()->instr_end(); + do ++MII; + while (MII != E && MII->isInsideBundle()); return *this; } bundle_iterator operator--(int) { // postdecrement operators... bundle_iterator tmp = *this; - do { - --MII; - } while (MII->isInsideBundle()); + --*this; return tmp; } bundle_iterator operator++(int) { // postincrement operators... bundle_iterator tmp = *this; - do { - ++MII; - } while (MII->isInsideBundle()); + ++*this; return tmp; } @@ -238,42 +230,14 @@ public: reverse_instr_iterator instr_rend () { return Insts.rend(); } const_reverse_instr_iterator instr_rend () const { return Insts.rend(); } - iterator begin() { return Insts.begin(); } - const_iterator begin() const { return Insts.begin(); } - iterator end() { - instr_iterator II = instr_end(); - if (II != instr_begin()) { - while (II->isInsideBundle()) - --II; - } - return II; - } - const_iterator end() const { - const_instr_iterator II = instr_end(); - if (II != instr_begin()) { - while (II->isInsideBundle()) - --II; - } - return II; - } - reverse_iterator rbegin() { - reverse_instr_iterator II = instr_rbegin(); - if (II != instr_rend()) { - while (II->isInsideBundle()) - ++II; - } - return II; - } - const_reverse_iterator rbegin() const { - const_reverse_instr_iterator II = instr_rbegin(); - if (II != instr_rend()) { - while (II->isInsideBundle()) - ++II; - } - return II; - } - reverse_iterator rend () { return Insts.rend(); } - const_reverse_iterator rend () const { return Insts.rend(); } + iterator begin() { return instr_begin(); } + const_iterator begin() const { return instr_begin(); } + iterator end () { return instr_end(); } + const_iterator end () const { return instr_end(); } + reverse_iterator rbegin() { return instr_rbegin(); } + const_reverse_iterator rbegin() const { return instr_rbegin(); } + reverse_iterator rend () { return instr_rend(); } + const_reverse_iterator rend () const { return instr_rend(); } // Machine-CFG iterators -- cgit v1.1 From 0eb3a3524e9d68642e574780d19c781386ed4469 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Mon, 11 Jun 2012 23:42:23 +0000 Subject: misched: When querying RegisterPressureTracker, always save current and max pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158340 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/RegisterPressure.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/RegisterPressure.h b/include/llvm/CodeGen/RegisterPressure.h index e810f8c..2043155 100644 --- a/include/llvm/CodeGen/RegisterPressure.h +++ b/include/llvm/CodeGen/RegisterPressure.h @@ -249,19 +249,22 @@ public: /// Get the pressure of each PSet after traversing this instruction bottom-up. void getUpwardPressure(const MachineInstr *MI, - std::vector &PressureResult); + std::vector &PressureResult, + std::vector &MaxPressureResult); /// Get the pressure of each PSet after traversing this instruction top-down. void getDownwardPressure(const MachineInstr *MI, - std::vector &PressureResult); + std::vector &PressureResult, + std::vector &MaxPressureResult); void getPressureAfterInst(const MachineInstr *MI, - std::vector &PressureResult) { + std::vector &PressureResult, + std::vector &MaxPressureResult) { if (isTopClosed()) - return getUpwardPressure(MI, PressureResult); + return getUpwardPressure(MI, PressureResult, MaxPressureResult); assert(isBottomClosed() && "Uninitialized pressure tracker"); - return getDownwardPressure(MI, PressureResult); + return getDownwardPressure(MI, PressureResult, MaxPressureResult); } protected: -- cgit v1.1 From 9df55eed0470c898c4003dc433c4479bdb0e0aac Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 13 Jun 2012 02:39:00 +0000 Subject: sched: Avoid trivially redundant DAG edges. Take the one with higher latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158379 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ScheduleDAG.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 3dd3c0c..85ab47b 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -117,8 +117,9 @@ namespace llvm { } } - bool operator==(const SDep &Other) const { - if (Dep != Other.Dep || Latency != Other.Latency) return false; + /// Return true if the specified SDep is equivalent except for latency. + bool overlaps(const SDep &Other) const { + if (Dep != Other.Dep) return false; switch (Dep.getInt()) { case Data: case Anti: @@ -133,6 +134,10 @@ namespace llvm { llvm_unreachable("Invalid dependency kind!"); } + bool operator==(const SDep &Other) const { + return overlaps(Other) && Latency == Other.Latency; + } + bool operator!=(const SDep &Other) const { return !operator==(Other); } -- cgit v1.1 From a9783663398baf1289683fc7326430b89963f38e Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 16 Jun 2012 21:48:13 +0000 Subject: Guard private fields that are unused in Release builds with #ifndef NDEBUG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158608 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LexicalScopes.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LexicalScopes.h b/include/llvm/CodeGen/LexicalScopes.h index eb01f66..8414c64 100644 --- a/include/llvm/CodeGen/LexicalScopes.h +++ b/include/llvm/CodeGen/LexicalScopes.h @@ -158,7 +158,10 @@ class LexicalScope { public: LexicalScope(LexicalScope *P, const MDNode *D, const MDNode *I, bool A) : Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A), - LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0), IndentLevel(0) { + LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0) { +#ifndef NDEBUG + IndentLevel = 0; +#endif if (Parent) Parent->addChild(this); } @@ -241,7 +244,9 @@ private: const MachineInstr *FirstInsn; // First instruction of this scope. unsigned DFSIn, DFSOut; // In & Out Depth use to determine // scope nesting. +#ifndef NDEBUG mutable unsigned IndentLevel; // Private state for dump() +#endif }; } // end llvm namespace -- cgit v1.1 From e877c4f9c7b4e4142f33a29e6cd1a07262525a12 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Mon, 18 Jun 2012 21:08:18 +0000 Subject: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158679 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/DFAPacketizer.h | 2 +- include/llvm/CodeGen/ScoreboardHazardRecognizer.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index 2d2db78..d9a48b6 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -42,7 +42,7 @@ class SUnit; class DFAPacketizer { private: - typedef std::pair UnsignPair; + typedef std::pair UnsignPair; const InstrItineraryData *InstrItins; int CurrentState; const int (*DFAStateInputTable)[2]; diff --git a/include/llvm/CodeGen/ScoreboardHazardRecognizer.h b/include/llvm/CodeGen/ScoreboardHazardRecognizer.h index 060e89a..c741e1b 100644 --- a/include/llvm/CodeGen/ScoreboardHazardRecognizer.h +++ b/include/llvm/CodeGen/ScoreboardHazardRecognizer.h @@ -39,7 +39,7 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer { // bottom-up scheduler, then the scoreboard cycles are the inverse of the // scheduler's cycles. class Scoreboard { - unsigned *Data; + uint64_t *Data; // The maximum number of cycles monitored by the Scoreboard. This // value is determined based on the target itineraries to ensure @@ -54,7 +54,7 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer { } size_t getDepth() const { return Depth; } - unsigned& operator[](size_t idx) const { + uint64_t& operator[](size_t idx) const { // Depth is expected to be a power-of-2. assert(Depth && !(Depth & (Depth - 1)) && "Scoreboard was not initialized properly!"); @@ -65,7 +65,7 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer { void reset(size_t d = 1) { if (Data == NULL) { Depth = d; - Data = new unsigned[Depth]; + Data = new uint64_t[Depth]; } memset(Data, 0, Depth * sizeof(Data[0])); -- cgit v1.1 From d6b43a317e71246380db55a50b799b062b53cdce Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Tue, 19 Jun 2012 00:48:28 +0000 Subject: Move the support for using .init_array from ARM to the generic TargetLoweringObjectFileELF. Use this to support it on X86. Unlike ARM, on X86 it is not easy to find out if .init_array should be used or not, so the decision is made via TargetOptions and defaults to off. Add a command line option to llc that enables it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158692 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/TargetLoweringObjectFileImpl.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h b/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h index 5a42136..9849e92 100644 --- a/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h +++ b/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h @@ -33,6 +33,8 @@ namespace llvm { class TargetLoweringObjectFileELF : public TargetLoweringObjectFile { + bool UseInitArray; + public: virtual ~TargetLoweringObjectFileELF() {} @@ -66,6 +68,7 @@ public: getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang, MachineModuleInfo *MMI) const; + void InitializeELF(bool UseInitArray_); virtual const MCSection * getStaticCtorSection(unsigned Priority = 65535) const; virtual const MCSection * -- cgit v1.1 From f54469f7fc505e15db48b20a902dacd9809f6529 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Tue, 19 Jun 2012 22:28:18 +0000 Subject: Typo. Patch by Cameron McInally . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158754 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ISDOpcodes.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index e380650..3a92e9a 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -585,8 +585,8 @@ namespace ISD { // DEBUGTRAP - Trap intended to get the attention of a debugger. DEBUGTRAP, - // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are - // their first operand. The other operands are the address to prefetch, + // PREFETCH - This corresponds to a prefetch intrinsic. The first operand + // is the chain. The other operands are the address to prefetch, // read / write specifier, locality specifier and instruction / data cache // specifier. PREFETCH, -- cgit v1.1 From 2531a6415ff9c082bb1c11c27f1b03aa3e1b97df Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Tue, 19 Jun 2012 22:59:12 +0000 Subject: Add an ensureMaxAlignment() function to MachineFrameInfo (analogous to ensureAlignment() in MachineFunction). Also, drop setMaxAlignment() in favor of this new function. This creates a main entry point to setting MaxAlignment, which will be helpful for future work. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158758 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineFrameInfo.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineFrameInfo.h b/include/llvm/CodeGen/MachineFrameInfo.h index 44402a9..8b958e4 100644 --- a/include/llvm/CodeGen/MachineFrameInfo.h +++ b/include/llvm/CodeGen/MachineFrameInfo.h @@ -359,7 +359,7 @@ public: assert(unsigned(ObjectIdx+NumFixedObjects) < Objects.size() && "Invalid Object Idx!"); Objects[ObjectIdx+NumFixedObjects].Alignment = Align; - MaxAlignment = std::max(MaxAlignment, Align); + ensureMaxAlignment(Align); } /// NeedsStackProtector - Returns true if the object may need stack @@ -416,9 +416,11 @@ public: /// unsigned getMaxAlignment() const { return MaxAlignment; } - /// setMaxAlignment - Set the preferred alignment. - /// - void setMaxAlignment(unsigned Align) { MaxAlignment = Align; } + /// ensureMaxAlignment - Make sure the function is at least Align bytes + /// aligned. + void ensureMaxAlignment(unsigned Align) { + if (MaxAlignment < Align) MaxAlignment = Align; + } /// AdjustsStack - Return true if this function adjusts the stack -- e.g., /// when calling another function. This is only valid during and after @@ -485,7 +487,7 @@ public: Objects.push_back(StackObject(Size, Alignment, 0, false, isSS, MayNeedSP)); int Index = (int)Objects.size() - NumFixedObjects - 1; assert(Index >= 0 && "Bad frame index!"); - MaxAlignment = std::max(MaxAlignment, Alignment); + ensureMaxAlignment(Alignment); return Index; } @@ -496,7 +498,7 @@ public: int CreateSpillStackObject(uint64_t Size, unsigned Alignment) { CreateStackObject(Size, Alignment, true, false); int Index = (int)Objects.size() - NumFixedObjects - 1; - MaxAlignment = std::max(MaxAlignment, Alignment); + ensureMaxAlignment(Alignment); return Index; } @@ -515,7 +517,7 @@ public: int CreateVariableSizedObject(unsigned Alignment) { HasVarSizedObjects = true; Objects.push_back(StackObject(0, Alignment, 0, false, false, true)); - MaxAlignment = std::max(MaxAlignment, Alignment); + ensureMaxAlignment(Alignment); return (int)Objects.size()-NumFixedObjects-1; } -- cgit v1.1 From 305b515c2787f47adecbe120e4b4bef55c5e5525 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Wed, 20 Jun 2012 08:39:33 +0000 Subject: Remove 'static' from inline functions defined in header files. There is a pretty staggering amount of this in LLVM's header files, this is not all of the instances I'm afraid. These include all of the functions that (in my build) are used by a non-static inline (or external) function. Specifically, these issues were caught by the new '-Winternal-linkage-in-inline' warning. I'll try to just clean up the remainder of the clearly redundant "static inline" cases on functions (not methods!) defined within headers if I can do so in a reliable way. There were even several cases of a missing 'inline' altogether, or my personal favorite "static bool inline". Go figure. ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158800 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstrBundle.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineInstrBundle.h b/include/llvm/CodeGen/MachineInstrBundle.h index 0fb4969..dc5f9a6 100644 --- a/include/llvm/CodeGen/MachineInstrBundle.h +++ b/include/llvm/CodeGen/MachineInstrBundle.h @@ -43,14 +43,14 @@ bool finalizeBundles(MachineFunction &MF); /// getBundleStart - Returns the first instruction in the bundle containing MI. /// -static inline MachineInstr *getBundleStart(MachineInstr *MI) { +inline MachineInstr *getBundleStart(MachineInstr *MI) { MachineBasicBlock::instr_iterator I = MI; while (I->isInsideBundle()) --I; return I; } -static inline const MachineInstr *getBundleStart(const MachineInstr *MI) { +inline const MachineInstr *getBundleStart(const MachineInstr *MI) { MachineBasicBlock::const_instr_iterator I = MI; while (I->isInsideBundle()) --I; -- cgit v1.1 From 7824152557cfe3a366963f504b2b956f853ebc3a Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 20 Jun 2012 18:00:57 +0000 Subject: Only update regunit live ranges that have been precomputed. Regunit live ranges are computed on demand, so when mi-sched calls handleMove, some regunits may not have live ranges yet. That makes updating them easier: Just skip the non-existing ranges. They will be computed correctly from the rescheduled machine code when they are needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158831 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index bd3604c..bb547c3 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -347,6 +347,12 @@ namespace llvm { return *LI; } + /// getCachedRegUnit - Return the live range for Unit if it has already + /// been computed, or NULL if it hasn't been computed yet. + LiveInterval *getCachedRegUnit(unsigned Unit) { + return RegUnitIntervals[Unit]; + } + /// trackingRegUnits - Does LiveIntervals curently track register units? /// This function will be removed when regunit tracking is permanently /// enabled. -- cgit v1.1 From 60c7d5bc2cbeff9eff16716295ffd6a5374dc6bc Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Wed, 20 Jun 2012 20:17:20 +0000 Subject: Add "extern template" declarations now that we use explicit instantiation. This is supported by gcc and clang, but guarded by a macro for MSVC 2008. The extern template declaration is not necessary but generally good form. It can avoid extra instantiations of the template methods defined inline. The EXTERN_TEMPLATE_INSTANTIATION macro could probably be generalized to handle multiple template parameters if someone thinks it's worthwhile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158840 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineLoopInfo.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineLoopInfo.h b/include/llvm/CodeGen/MachineLoopInfo.h index 6dd9440..3e204be 100644 --- a/include/llvm/CodeGen/MachineLoopInfo.h +++ b/include/llvm/CodeGen/MachineLoopInfo.h @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines the MachineLoopInfo class that is used to identify natural +// This file defines the MachineLoopInfo class that is used to identify natural // loops and determine the loop depth of various nodes of the CFG. Note that // natural loops may actually be several loops that share the same header node. // @@ -35,6 +35,12 @@ namespace llvm { +// Implementation in LoopInfoImpl.h +#ifdef __GNUC__ +class MachineLoop; +__extension__ extern template class LoopBase; +#endif + class MachineLoop : public LoopBase { public: MachineLoop(); @@ -57,6 +63,12 @@ private: : LoopBase(MBB) {} }; +// Implementation in LoopInfoImpl.h +#ifdef __GNUC__ +__extension__ extern template +class LoopInfoBase; +#endif + class MachineLoopInfo : public MachineFunctionPass { LoopInfoBase LI; friend class LoopBase; -- cgit v1.1 From 895fe245578830881744826b04da4788ff614853 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 20 Jun 2012 23:54:20 +0000 Subject: Remove LiveIntervals::iterator. Live intervals for regunits and virtual registers are stored separately, and physreg live intervals are going away. To visit the live ranges of all virtual registers, use this pattern instead: for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { unsigned Reg = TargetRegisterInfo::index2VirtReg(i); if (MRI->reg_nodbg_empty(Reg)) continue; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158879 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index bb547c3..fa7dca9 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -108,12 +108,6 @@ namespace llvm { // Calculate the spill weight to assign to a single instruction. static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth); - typedef Reg2IntervalMap::iterator iterator; - typedef Reg2IntervalMap::const_iterator const_iterator; - const_iterator begin() const { return R2IMap.begin(); } - const_iterator end() const { return R2IMap.end(); } - iterator begin() { return R2IMap.begin(); } - iterator end() { return R2IMap.end(); } unsigned getNumIntervals() const { return (unsigned)R2IMap.size(); } LiveInterval &getInterval(unsigned reg) { -- cgit v1.1 From ffccd923101ae177c1a2c407618d8f03a312d69b Mon Sep 17 00:00:00 2001 From: Nick Lewycky Date: Fri, 22 Jun 2012 01:25:12 +0000 Subject: Emit relocations for DW_AT_location entries on systems which need it. This is a recommit of r127757. Fixes PR9493. Patch by Paul Robinson! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158957 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/AsmPrinter.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h index 56a87f1..170a528 100644 --- a/include/llvm/CodeGen/AsmPrinter.h +++ b/include/llvm/CodeGen/AsmPrinter.h @@ -354,6 +354,13 @@ namespace llvm { void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset, unsigned Size) const; + /// EmitLabelReference - Emit something like ".long Label" + /// where the size in bytes of the directive is specified by Size and Label + /// specifies the label. + void EmitLabelReference(const MCSymbol *Label, unsigned Size) const { + EmitLabelPlusOffset(Label, 0, Size); + } + //===------------------------------------------------------------------===// // Dwarf Emission Helper Routines //===------------------------------------------------------------------===// -- cgit v1.1 From 63e0e8d90b6a2f41601097c47e37836fba7506d8 Mon Sep 17 00:00:00 2001 From: Dmitri Gribenko Date: Fri, 22 Jun 2012 16:00:48 +0000 Subject: Change comment into proper Doxygen member comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159000 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/GCMetadata.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/GCMetadata.h b/include/llvm/CodeGen/GCMetadata.h index 2b6c35b..20e33f7 100644 --- a/include/llvm/CodeGen/GCMetadata.h +++ b/include/llvm/CodeGen/GCMetadata.h @@ -71,7 +71,8 @@ namespace llvm { struct GCRoot { int Num; ///< Usually a frame index. int StackOffset; ///< Offset from the stack pointer. - const Constant *Metadata;//< Metadata straight from the call to llvm.gcroot. + const Constant *Metadata; ///< Metadata straight from the call + ///< to llvm.gcroot. GCRoot(int N, const Constant *MD) : Num(N), StackOffset(-1), Metadata(MD) {} }; -- cgit v1.1 From 241d0209a765c97c684b120527e185f17723f650 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 22 Jun 2012 16:46:44 +0000 Subject: Remove LiveIntervals::trackingRegUnits(). With regunit liveness permanently enabled, this function would always return true. Also remove now obsolete code for checking physreg interference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159006 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index fa7dca9..3519a5d 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -347,11 +347,6 @@ namespace llvm { return RegUnitIntervals[Unit]; } - /// trackingRegUnits - Does LiveIntervals curently track register units? - /// This function will be removed when regunit tracking is permanently - /// enabled. - bool trackingRegUnits() const { return !RegUnitIntervals.empty(); } - private: /// computeIntervals - Compute live intervals. void computeIntervals(); -- cgit v1.1 From 27b7669a6058235eec494ea30d0d62b7146e0eb4 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 22 Jun 2012 18:20:50 +0000 Subject: Stop computing physreg live ranges. Everyone is using on-demand regunit ranges now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159018 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 3519a5d..2e539fa 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -352,8 +352,7 @@ namespace llvm { void computeIntervals(); /// handleRegisterDef - update intervals for a register def - /// (calls handlePhysicalRegisterDef and - /// handleVirtualRegisterDef) + /// (calls handleVirtualRegisterDef) void handleRegisterDef(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI, SlotIndex MIIdx, @@ -373,18 +372,6 @@ namespace llvm { unsigned MOIdx, LiveInterval& interval); - /// handlePhysicalRegisterDef - update intervals for a physical register - /// def. - void handlePhysicalRegisterDef(MachineBasicBlock* mbb, - MachineBasicBlock::iterator mi, - SlotIndex MIIdx, MachineOperand& MO, - LiveInterval &interval); - - /// handleLiveInRegister - Create interval for a livein register. - void handleLiveInRegister(MachineBasicBlock* mbb, - SlotIndex MIIdx, - LiveInterval &interval); - static LiveInterval* createInterval(unsigned Reg); void printInstrs(raw_ostream &O) const; -- cgit v1.1 From b460a3382961c5be9952a75d46228f624edbd39f Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Fri, 22 Jun 2012 20:27:13 +0000 Subject: Revert r158679 - use case is unclear (and it increases the memory footprint). Original commit message: Allow up to 64 functional units per processor itinerary. This patch changes the type used to hold the FU bitset from unsigned to uint64_t. This will be needed for some upcoming PowerPC itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159027 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/DFAPacketizer.h | 2 +- include/llvm/CodeGen/ScoreboardHazardRecognizer.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index d9a48b6..2d2db78 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -42,7 +42,7 @@ class SUnit; class DFAPacketizer { private: - typedef std::pair UnsignPair; + typedef std::pair UnsignPair; const InstrItineraryData *InstrItins; int CurrentState; const int (*DFAStateInputTable)[2]; diff --git a/include/llvm/CodeGen/ScoreboardHazardRecognizer.h b/include/llvm/CodeGen/ScoreboardHazardRecognizer.h index c741e1b..060e89a 100644 --- a/include/llvm/CodeGen/ScoreboardHazardRecognizer.h +++ b/include/llvm/CodeGen/ScoreboardHazardRecognizer.h @@ -39,7 +39,7 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer { // bottom-up scheduler, then the scoreboard cycles are the inverse of the // scheduler's cycles. class Scoreboard { - uint64_t *Data; + unsigned *Data; // The maximum number of cycles monitored by the Scoreboard. This // value is determined based on the target itineraries to ensure @@ -54,7 +54,7 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer { } size_t getDepth() const { return Depth; } - uint64_t& operator[](size_t idx) const { + unsigned& operator[](size_t idx) const { // Depth is expected to be a power-of-2. assert(Depth && !(Depth & (Depth - 1)) && "Scoreboard was not initialized properly!"); @@ -65,7 +65,7 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer { void reset(size_t d = 1) { if (Data == NULL) { Depth = d; - Data = new uint64_t[Depth]; + Data = new unsigned[Depth]; } memset(Data, 0, Depth * sizeof(Data[0])); -- cgit v1.1 From 7fa6784296e6bc1aa4e8ec3664e58247893c21a2 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 22 Jun 2012 20:37:52 +0000 Subject: Store live intervals in an IndexedMap. It is both smaller and faster than DenseMap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159029 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 54 ++++++++++++++--------------- 1 file changed, 26 insertions(+), 28 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 2e539fa..a941cc0 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -20,12 +20,13 @@ #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/LiveInterval.h" #include "llvm/CodeGen/SlotIndexes.h" #include "llvm/ADT/BitVector.h" -#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/IndexedMap.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Allocator.h" @@ -61,8 +62,8 @@ namespace llvm { /// VNInfo::Allocator VNInfoAllocator; - typedef DenseMap Reg2IntervalMap; - Reg2IntervalMap R2IMap; + /// Live interval pointers for all the virtual registers. + IndexedMap VirtRegIntervals; /// AllocatableRegs - A bit vector of allocatable registers. BitVector AllocatableRegs; @@ -108,22 +109,20 @@ namespace llvm { // Calculate the spill weight to assign to a single instruction. static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth); - unsigned getNumIntervals() const { return (unsigned)R2IMap.size(); } + unsigned getNumIntervals() const { return (unsigned)VirtRegIntervals.size(); } - LiveInterval &getInterval(unsigned reg) { - Reg2IntervalMap::iterator I = R2IMap.find(reg); - assert(I != R2IMap.end() && "Interval does not exist for register"); - return *I->second; + LiveInterval &getInterval(unsigned Reg) { + LiveInterval *LI = VirtRegIntervals[Reg]; + assert(LI && "Interval does not exist for virtual register"); + return *LI; } - const LiveInterval &getInterval(unsigned reg) const { - Reg2IntervalMap::const_iterator I = R2IMap.find(reg); - assert(I != R2IMap.end() && "Interval does not exist for register"); - return *I->second; + const LiveInterval &getInterval(unsigned Reg) const { + return const_cast(this)->getInterval(Reg); } - bool hasInterval(unsigned reg) const { - return R2IMap.count(reg); + bool hasInterval(unsigned Reg) const { + return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg]; } /// isAllocatable - is the physical register reg allocatable in the current @@ -138,12 +137,19 @@ namespace llvm { return ReservedRegs.test(reg); } - // Interval creation - LiveInterval &getOrCreateInterval(unsigned reg) { - Reg2IntervalMap::iterator I = R2IMap.find(reg); - if (I == R2IMap.end()) - I = R2IMap.insert(std::make_pair(reg, createInterval(reg))).first; - return *I->second; + // Interval creation. + LiveInterval &getOrCreateInterval(unsigned Reg) { + if (!hasInterval(Reg)) { + VirtRegIntervals.grow(Reg); + VirtRegIntervals[Reg] = createInterval(Reg); + } + return getInterval(Reg); + } + + // Interval removal. + void removeInterval(unsigned Reg) { + delete VirtRegIntervals[Reg]; + VirtRegIntervals[Reg] = 0; } /// addLiveRangeToEndOfBlock - Given a register and an instruction, @@ -161,14 +167,6 @@ namespace llvm { bool shrinkToUses(LiveInterval *li, SmallVectorImpl *dead = 0); - // Interval removal - - void removeInterval(unsigned Reg) { - DenseMap::iterator I = R2IMap.find(Reg); - delete I->second; - R2IMap.erase(I); - } - SlotIndexes *getSlotIndexes() const { return Indexes; } -- cgit v1.1 From bfd752f310078561de07850ce66213c4579a0d7e Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 22 Jun 2012 20:40:15 +0000 Subject: Delete a boring statistic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159030 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveIntervalAnalysis.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index a941cc0..a344b1f 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -109,8 +109,6 @@ namespace llvm { // Calculate the spill weight to assign to a single instruction. static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth); - unsigned getNumIntervals() const { return (unsigned)VirtRegIntervals.size(); } - LiveInterval &getInterval(unsigned Reg) { LiveInterval *LI = VirtRegIntervals[Reg]; assert(LI && "Interval does not exist for virtual register"); -- cgit v1.1 From 0cafa139c01aa9d5072b185d686a05b9d8ab1ee7 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 22 Jun 2012 22:27:36 +0000 Subject: Remove ProcessImplicitDefs.h which was unused. The ProcessImplicitDefs class can be local to its implementation file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159041 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ProcessImplicitDefs.h | 51 ------------------------------ 1 file changed, 51 deletions(-) delete mode 100644 include/llvm/CodeGen/ProcessImplicitDefs.h (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ProcessImplicitDefs.h b/include/llvm/CodeGen/ProcessImplicitDefs.h deleted file mode 100644 index 6ab57f0..0000000 --- a/include/llvm/CodeGen/ProcessImplicitDefs.h +++ /dev/null @@ -1,51 +0,0 @@ -//===-------------- llvm/CodeGen/ProcessImplicitDefs.h ----------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - - -#ifndef LLVM_CODEGEN_PROCESSIMPLICITDEFS_H -#define LLVM_CODEGEN_PROCESSIMPLICITDEFS_H - -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/ADT/SmallSet.h" - -namespace llvm { - - class MachineInstr; - class TargetInstrInfo; - class TargetRegisterInfo; - class MachineRegisterInfo; - class LiveVariables; - - /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def - /// for each use. Add isUndef marker to implicit_def defs and their uses. - class ProcessImplicitDefs : public MachineFunctionPass { - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; - MachineRegisterInfo *MRI; - LiveVariables *LV; - - bool CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg, - unsigned OpIdx, - SmallSet &ImpDefRegs); - - public: - static char ID; - - ProcessImplicitDefs() : MachineFunctionPass(ID) { - initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry()); - } - - virtual void getAnalysisUsage(AnalysisUsage &au) const; - - virtual bool runOnMachineFunction(MachineFunction &fn); - }; - -} - -#endif // LLVM_CODEGEN_PROCESSIMPLICITDEFS_H -- cgit v1.1 From 34f5a2b596236a5452ddc664066138ca7a0c7af2 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 26 Jun 2012 17:09:29 +0000 Subject: Allow targets to inject passes before the virtual register rewriter. Such passes can be used to tweak the register assignments in a target-dependent way, for example to avoid write-after-write dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159209 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index cc3b3d7..206bc2e 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -175,6 +175,18 @@ protected: /// LLVMTargetMachine provides standard regalloc passes for most targets. virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass); + /// addPreRewrite - Add passes to the optimized register allocation pipeline + /// after register allocation is complete, but before virtual registers are + /// rewritten to physical registers. + /// + /// These passes must preserve VirtRegMap and LiveIntervals, and when running + /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. + /// When these passes run, VirtRegMap contains legal physreg assignments for + /// all virtual registers. + virtual bool addPreRewrite() { + return false; + } + /// addFinalizeRegAlloc - This method may be implemented by targets that want /// to run passes within the regalloc pipeline, immediately after the register /// allocation pass itself. These passes run as soon as virtual regisiters -- cgit v1.1 From 54d69668b22b8c37aa6e45f14445f3988cc430d4 Mon Sep 17 00:00:00 2001 From: Manman Ren Date: Fri, 29 Jun 2012 19:16:05 +0000 Subject: Add getUniqueVRegDef to MachineRegisterInfo. This comes in handy during peephole optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159453 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineRegisterInfo.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h index 5a82caa..2bcd1c7 100644 --- a/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/include/llvm/CodeGen/MachineRegisterInfo.h @@ -237,6 +237,11 @@ public: /// form, so there should only be one definition. MachineInstr *getVRegDef(unsigned Reg) const; + /// getUniqueVRegDef - Return the unique machine instr that defines the + /// specified virtual register or null if none is found. If there are + /// multiple definitions or no definition, return null. + MachineInstr *getUniqueVRegDef(unsigned Reg) const; + /// clearKillFlags - Iterate over all the uses of the given register and /// clear the kill flag from the MachineOperand. This function is used by /// optimization passes which extend register lifetimes and need only -- cgit v1.1 From 8add7b48d2c548299d9d590ad048ca1637b170c6 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Mon, 2 Jul 2012 19:48:18 +0000 Subject: Add a missing forward declaration of PassManagerBase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159566 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 206bc2e..b0de2dc 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -24,6 +24,7 @@ namespace llvm { class FunctionPass; class MachineFunctionPass; class PassInfo; + class PassManagerBase; class TargetLowering; class TargetRegisterClass; class raw_ostream; -- cgit v1.1 From 564fbf6aff8fb95646a1290078a37c2d4dbe629f Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Mon, 2 Jul 2012 19:48:31 +0000 Subject: Add all codegen passes to the PassManager via TargetPassConfig. This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index b0de2dc..1ccf29d 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -55,9 +55,11 @@ public: /// optimization after regalloc. static char PostRAMachineLICMID; +private: + PassManagerBase *PM; + protected: TargetMachine *TM; - PassManagerBase *PM; PassConfigImpl *Impl; // Internal data structures bool Initialized; // Flagged after all passes are configured. @@ -122,6 +124,9 @@ public: /// transforms following machine independent optimization. virtual void addIRPasses(); + /// Add passes to lower exception handling for the code generator. + void addPassesToHandleExceptions(); + /// Add common passes that perform LLVM IR to IR transforms in preparation for /// instruction selection. virtual void addISelPrepare(); @@ -235,6 +240,9 @@ protected: /// Return the pass that was added, or NoPassID. AnalysisID addPass(char &ID); + /// Add a pass to the PassManager. + void addPass(Pass *P); + /// addMachinePasses helper to create the target-selected or overriden /// regalloc pass. FunctionPass *createRegAllocPass(bool Optimized); @@ -242,7 +250,7 @@ protected: /// printAndVerify - Add a pass to dump then verify the machine function, if /// those steps are enabled. /// - void printAndVerify(const char *Banner) const; + void printAndVerify(const char *Banner); }; } // namespace llvm -- cgit v1.1 From 3fb99a73686c39d9855b3f8881add977af3868cb Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Mon, 2 Jul 2012 19:48:37 +0000 Subject: Consistently use AnalysisID types in TargetPassConfig. This makes it possible to just use a zero value to represent "no pass", so the phony NoPassID global variable is no longer needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159568 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineScheduler.h | 2 +- include/llvm/CodeGen/Passes.h | 18 ++++++++---------- 2 files changed, 9 insertions(+), 11 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h index e5d3a98..8da2045 100644 --- a/include/llvm/CodeGen/MachineScheduler.h +++ b/include/llvm/CodeGen/MachineScheduler.h @@ -19,7 +19,7 @@ // createCustomMachineSched); // // Inside PassConfig: -// enablePass(MachineSchedulerID); +// enablePass(&MachineSchedulerID); // MachineSchedRegistry::setDefault(createCustomMachineSched); // //===----------------------------------------------------------------------===// diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 1ccf29d..b7c81af 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -32,8 +32,6 @@ namespace llvm { namespace llvm { -extern char &NoPassID; // Allow targets to choose not to run a pass. - class PassConfigImpl; /// Target-Independent Code Generator Pass Configuration Options. @@ -101,19 +99,19 @@ public: /// Allow the target to override a specific pass without overriding the pass /// pipeline. When passes are added to the standard pipeline at the - /// point where StadardID is expected, add TargetID in its place. - void substitutePass(char &StandardID, char &TargetID); + /// point where StandardID is expected, add TargetID in its place. + void substitutePass(AnalysisID StandardID, AnalysisID TargetID); /// Insert InsertedPassID pass after TargetPassID pass. - void insertPass(const char &TargetPassID, const char &InsertedPassID); + void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID); /// Allow the target to enable a specific standard pass by default. - void enablePass(char &ID) { substitutePass(ID, ID); } + void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); } /// Allow the target to disable a specific standard pass by default. - void disablePass(char &ID) { substitutePass(ID, NoPassID); } + void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); } - /// Return the pass ssubtituted for StandardID by the target. + /// Return the pass substituted for StandardID by the target. /// If no substitution exists, return StandardID. AnalysisID getPassSubstitution(AnalysisID StandardID) const; @@ -237,8 +235,8 @@ protected: /// /// Add a CodeGen pass at this point in the pipeline after checking overrides. - /// Return the pass that was added, or NoPassID. - AnalysisID addPass(char &ID); + /// Return the pass that was added, or zero if no pass was added. + AnalysisID addPass(AnalysisID PassID); /// Add a pass to the PassManager. void addPass(Pass *P); -- cgit v1.1 From 30a507a1f5d6a5646dd3481eba6958424415c886 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Mon, 2 Jul 2012 19:48:45 +0000 Subject: Extend TargetPassConfig to allow running only a subset of the normal passes. This is still a work in progress but I believe it is currently good enough to fix PR13122 "Need unit test driver for codegen IR passes". For example, you can run llc with -stop-after=loop-reduce to have it dump out the IR after running LSR. Serializing machine-level IR is not yet supported but we have some patches in progress for that. The plan is to serialize the IR to a YAML file, containing separate sections for the LLVM IR, machine-level IR, and whatever other info is needed. Chad suggested that we stash the stop-after pass in the YAML file and use that instead of the start-after option to figure out where to restart the compilation. I think that's a great idea, but since it's not implemented yet I put the -start-after option into this patch for testing purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159570 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index b7c81af..4a24ab0 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -55,6 +55,10 @@ public: private: PassManagerBase *PM; + AnalysisID StartAfter; + AnalysisID StopAfter; + bool Started; + bool Stopped; protected: TargetMachine *TM; @@ -92,6 +96,18 @@ public: CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); } + /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow + /// running only a portion of the normal code-gen pass sequence. If the + /// Start pass ID is zero, then compilation will begin at the normal point; + /// otherwise, clear the Started flag to indicate that passes should not be + /// added until the starting pass is seen. If the Stop pass ID is zero, + /// then compilation will continue to the end. + void setStartStopPasses(AnalysisID Start, AnalysisID Stop) { + StartAfter = Start; + StopAfter = Stop; + Started = (StartAfter == 0); + } + void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); } bool getEnableTailMerge() const { return EnableTailMerge; } @@ -238,7 +254,8 @@ protected: /// Return the pass that was added, or zero if no pass was added. AnalysisID addPass(AnalysisID PassID); - /// Add a pass to the PassManager. + /// Add a pass to the PassManager if that pass is supposed to be run, as + /// determined by the StartAfter and StopAfter options. void addPass(Pass *P); /// addMachinePasses helper to create the target-selected or overriden -- cgit v1.1 From 33242fd3ed5586091e73254b58dd1825e9d53c60 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 4 Jul 2012 00:09:54 +0000 Subject: Add an experimental early if-conversion pass, off by default. This pass performs if-conversion on SSA form machine code by speculatively executing both sides of the branch and using a cmov instruction to select the result. This can help lower the number of branch mispredictions on architectures like x86 that don't have predicable instructions. The current implementation is very aggressive, and causes regressions on mosts tests. It needs good heuristics that have yet to be implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159694 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/Passes.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 4a24ab0..c80f6dc 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -392,6 +392,10 @@ namespace llvm { /// into tails of their predecessors. extern char &TailDuplicateID; + /// EarlyIfConverter - This pass performs if-conversion on SSA form by + /// inserting cmov instructions. + extern char &EarlyIfConverterID; + /// IfConverter - This pass performs machine code if conversion. extern char &IfConverterID; -- cgit v1.1 From d862d697d2d6f7d4e8fdd0b70686a6695e04d362 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Thu, 5 Jul 2012 11:06:22 +0000 Subject: Finish fixing the MachineOperand hashing, providing a nice modern hash_value overload for MachineOperands. This addresses a FIXME sufficient for me to remove it, and cleans up the code nicely too. The important changes to the hashing logic: - TargetFlags are now included in all of the hashes. These were complete missed. - Register operands have their subregisters and whether they are a def included in the hash. - We now actually hash all of the operand types. Previously, many operand types were simply *dropped on the floor*. For example: - Floating point immediates - Large integer immediates (>64-bit) - External globals! - Register masks - Metadata operands - It removes the offset from the block-address hash; I'm a bit suspicious of this, but isIdenticalTo doesn't consider the offset for black addresses. Any patterns involving these entities could have triggered extreme slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs you think might be closed now... I'm looking myself, but I may miss them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159743 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineOperand.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index 9ccbfe9..c3b4f7c 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -14,6 +14,7 @@ #ifndef LLVM_CODEGEN_MACHINEOPERAND_H #define LLVM_CODEGEN_MACHINEOPERAND_H +#include "llvm/ADT/Hashing.h" #include "llvm/Support/DataTypes.h" #include @@ -503,6 +504,13 @@ public: /// operand. Note: This method ignores isKill and isDead properties. bool isIdenticalTo(const MachineOperand &Other) const; + /// \brief MachineOperand hash_value overload. + /// + /// Note that this includes the same information in the hash that + /// isIdenticalTo uses for comparison. It is thus suited for use in hash + /// tables which use that function for equality comparisons only. + friend hash_code hash_value(const MachineOperand &MO); + /// ChangeToImmediate - Replace this operand with a new immediate operand of /// the specified value. If an operand is known to be an immediate already, /// the setImm method should be used. -- cgit v1.1 From 39c2a3d219021c14a4dd2552cc0b277fd0e3f702 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Thu, 5 Jul 2012 11:40:23 +0000 Subject: Remove dead infrastructure for building DenseMaps with a SlotIndex as the key -- they are now stored in an IntervalMap. I noticed this while looking into PR12652. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159745 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SlotIndexes.h | 31 ------------------------------- 1 file changed, 31 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/SlotIndexes.h b/include/llvm/CodeGen/SlotIndexes.h index c7fa512..8c56775 100644 --- a/include/llvm/CodeGen/SlotIndexes.h +++ b/include/llvm/CodeGen/SlotIndexes.h @@ -76,7 +76,6 @@ namespace llvm { /// SlotIndex - An opaque wrapper around machine indexes. class SlotIndex { friend class SlotIndexes; - friend struct DenseMapInfo; enum Slot { /// Basic block boundary. Used for live ranges entering and leaving a @@ -121,11 +120,6 @@ namespace llvm { return static_cast(lie.getInt()); } - static inline unsigned getHashValue(const SlotIndex &v) { - void *ptrVal = v.lie.getOpaqueValue(); - return (unsigned((intptr_t)ptrVal)) ^ (unsigned((intptr_t)ptrVal) >> 9); - } - public: enum { /// The default distance between instructions as returned by distance(). @@ -133,14 +127,6 @@ namespace llvm { InstrDist = 4 * Slot_Count }; - static inline SlotIndex getEmptyKey() { - return SlotIndex(0, 1); - } - - static inline SlotIndex getTombstoneKey() { - return SlotIndex(0, 2); - } - /// Construct an invalid index. SlotIndex() : lie(0, 0) {} @@ -293,23 +279,6 @@ namespace llvm { }; - /// DenseMapInfo specialization for SlotIndex. - template <> - struct DenseMapInfo { - static inline SlotIndex getEmptyKey() { - return SlotIndex::getEmptyKey(); - } - static inline SlotIndex getTombstoneKey() { - return SlotIndex::getTombstoneKey(); - } - static inline unsigned getHashValue(const SlotIndex &v) { - return SlotIndex::getHashValue(v); - } - static inline bool isEqual(const SlotIndex &LHS, const SlotIndex &RHS) { - return (LHS == RHS); - } - }; - template <> struct isPodLike { static const bool value = true; }; -- cgit v1.1 From 70cfaa34645bf8ad232c400f0fe7c48a9d715586 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 6 Jul 2012 23:13:38 +0000 Subject: Fix the naming of ensureAlignment. Per the coding standard function names should be camel case, and start with a lower case letter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159877 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineFunction.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h index dda2dc7..062c750 100644 --- a/include/llvm/CodeGen/MachineFunction.h +++ b/include/llvm/CodeGen/MachineFunction.h @@ -189,8 +189,8 @@ public: /// void setAlignment(unsigned A) { Alignment = A; } - /// EnsureAlignment - Make sure the function is at least 1 << A bytes aligned. - void EnsureAlignment(unsigned A) { + /// ensureAlignment - Make sure the function is at least 1 << A bytes aligned. + void ensureAlignment(unsigned A) { if (Alignment < A) Alignment = A; } -- cgit v1.1 From 261b6330896736f674bdb2dd4556a0483f3cfe8d Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Tue, 10 Jul 2012 05:06:03 +0000 Subject: Teach LiveIntervals how to verify themselves and start using it in some of the trick merge routines. This adds a layer of testing that was necessary when implementing more efficient (and complex) merge logic for this datastructure. No functionality changed here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159981 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 30acaff..e26a47a 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -489,6 +489,15 @@ namespace llvm { void print(raw_ostream &OS) const; void dump() const; + /// \brief Walk the interval and assert if any invariants fail to hold. + /// + /// Note that this is a no-op when asserts are disabled. +#ifdef NDEBUG + void verify() const {} +#else + void verify() const; +#endif + private: Ranges::iterator addRangeFrom(LiveRange LR, Ranges::iterator From); -- cgit v1.1 From e585e75612ef5fd32e2bb2c9f635496791a20f8b Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Tue, 10 Jul 2012 05:16:17 +0000 Subject: Add an efficient merge operation to LiveInterval and use it to avoid quadratic behavior when performing pathological merges. Fixes the core element of PR12652. There is only one user of addRangeFrom left: join. I'm hoping to refactor further in a future patch and have join use this merge operation as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159982 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index e26a47a..83a3b43 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -504,6 +504,9 @@ namespace llvm { void extendIntervalEndTo(Ranges::iterator I, SlotIndex NewEnd); Ranges::iterator extendIntervalStartTo(Ranges::iterator I, SlotIndex NewStr); void markValNoForDeletion(VNInfo *V); + void mergeIntervalRanges(const LiveInterval &RHS, + VNInfo *LHSValNo, + const VNInfo *RHSValNo = 0); LiveInterval& operator=(const LiveInterval& rhs); // DO NOT IMPLEMENT -- cgit v1.1 From 3f0dbab963197cadb32f70e1ee1a106fe35f5c8e Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Tue, 10 Jul 2012 17:45:53 +0000 Subject: Add support for dynamic stack realignment in the presence of dynamic allocas on X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineFrameInfo.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineFrameInfo.h b/include/llvm/CodeGen/MachineFrameInfo.h index 8b958e4..78898a4 100644 --- a/include/llvm/CodeGen/MachineFrameInfo.h +++ b/include/llvm/CodeGen/MachineFrameInfo.h @@ -215,6 +215,10 @@ class MachineFrameInfo { /// just allocate them normally. bool UseLocalStackAllocationBlock; + /// After the stack pointer has been restore from the base pointer we + /// use a cached adjusment. Currently only used for x86. + int64_t BPAdj; + public: explicit MachineFrameInfo(const TargetFrameLowering &tfi) : TFI(tfi) { StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0; @@ -230,6 +234,7 @@ public: LocalFrameSize = 0; LocalFrameMaxAlign = 0; UseLocalStackAllocationBlock = false; + BPAdj = 0; } /// hasStackObjects - Return true if there are any stack objects in this @@ -538,6 +543,16 @@ public: void setCalleeSavedInfoValid(bool v) { CSIValid = v; } + /// setBasePtrStackAdjustment - If we're restoring the stack pointer from the + /// base pointer, due to dynamic stack realignment + VLAs, we cache the + /// number of bytes initially allocated for the stack frame. In obscure + /// cases (e.g., tail calls with byval argument and no stack protector), the + /// stack gets adjusted outside of the prolog, but these shouldn't be + /// considered when restoring from the base pointer. Currently, this is only + /// needed for x86. + void setBasePtrStackAdjustment(int64_t adj) { BPAdj = adj; } + int64_t getBasePtrStackAdjustment() const { return BPAdj; } + /// getPristineRegs - Return a set of physical registers that are pristine on /// entry to the MBB. /// -- cgit v1.1 From 2b02688b6eee1340cb916934182a02698eea9f36 Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Tue, 10 Jul 2012 18:27:15 +0000 Subject: Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo to X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineFrameInfo.h | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/MachineFrameInfo.h b/include/llvm/CodeGen/MachineFrameInfo.h index 78898a4..8b958e4 100644 --- a/include/llvm/CodeGen/MachineFrameInfo.h +++ b/include/llvm/CodeGen/MachineFrameInfo.h @@ -215,10 +215,6 @@ class MachineFrameInfo { /// just allocate them normally. bool UseLocalStackAllocationBlock; - /// After the stack pointer has been restore from the base pointer we - /// use a cached adjusment. Currently only used for x86. - int64_t BPAdj; - public: explicit MachineFrameInfo(const TargetFrameLowering &tfi) : TFI(tfi) { StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0; @@ -234,7 +230,6 @@ public: LocalFrameSize = 0; LocalFrameMaxAlign = 0; UseLocalStackAllocationBlock = false; - BPAdj = 0; } /// hasStackObjects - Return true if there are any stack objects in this @@ -543,16 +538,6 @@ public: void setCalleeSavedInfoValid(bool v) { CSIValid = v; } - /// setBasePtrStackAdjustment - If we're restoring the stack pointer from the - /// base pointer, due to dynamic stack realignment + VLAs, we cache the - /// number of bytes initially allocated for the stack frame. In obscure - /// cases (e.g., tail calls with byval argument and no stack protector), the - /// stack gets adjusted outside of the prolog, but these shouldn't be - /// considered when restoring from the base pointer. Currently, this is only - /// needed for x86. - void setBasePtrStackAdjustment(int64_t adj) { BPAdj = adj; } - int64_t getBasePtrStackAdjustment() const { return BPAdj; } - /// getPristineRegs - Return a set of physical registers that are pristine on /// entry to the MBB. /// -- cgit v1.1 From 4e996de58cfad27033165d8feb8f296b8cbe20ca Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Tue, 10 Jul 2012 22:25:21 +0000 Subject: Teach the LiveInterval::join function to use the fast merge algorithm, generalizing its implementation sufficiently to support this value number scenario as well. This cuts out another significant performance hit in large functions (over 10k basic blocks, etc), especially those with "natural" CFG structures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/LiveInterval.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 83a3b43..3fe7c8d 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -505,7 +505,7 @@ namespace llvm { Ranges::iterator extendIntervalStartTo(Ranges::iterator I, SlotIndex NewStr); void markValNoForDeletion(VNInfo *V); void mergeIntervalRanges(const LiveInterval &RHS, - VNInfo *LHSValNo, + VNInfo *LHSValNo = 0, const VNInfo *RHSValNo = 0); LiveInterval& operator=(const LiveInterval& rhs); // DO NOT IMPLEMENT -- cgit v1.1 From b87bdac6a3de4ab83e23bf808f990e4bb7eade5e Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Sun, 15 Jul 2012 08:38:23 +0000 Subject: Refactor the code that checks that all operands of a node are UNDEFs. Add a micro-optimization to getNode of CONCAT_VECTORS when both operands are undefs. Can't find a testcase for this because VECTOR_SHUFFLE already handles undef operands, but Duncan suggested that we add this. Together with Michael Kuperstein git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160229 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SelectionDAGNodes.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h index f8248b8..41407f1 100644 --- a/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/include/llvm/CodeGen/SelectionDAGNodes.h @@ -74,6 +74,10 @@ namespace ISD { /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low /// element is not an undef. bool isScalarToVector(const SDNode *N); + + /// allOperandsUndef - Return true if the node has at least one operand + /// and all operands of the specified node are ISD::UNDEF. + bool allOperandsUndef(const SDNode *N); } // end llvm:ISD namespace //===----------------------------------------------------------------------===// -- cgit v1.1 From c8e41c591741b3da1077f7000274ad040bef8002 Mon Sep 17 00:00:00 2001 From: Sylvestre Ledru Date: Mon, 23 Jul 2012 08:51:15 +0000 Subject: Fix a typo (the the => the) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/SlotIndexes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/SlotIndexes.h b/include/llvm/CodeGen/SlotIndexes.h index 8c56775..c52599b 100644 --- a/include/llvm/CodeGen/SlotIndexes.h +++ b/include/llvm/CodeGen/SlotIndexes.h @@ -399,7 +399,7 @@ namespace llvm { } /// getIndexBefore - Returns the index of the last indexed instruction - /// before MI, or the the start index of its basic block. + /// before MI, or the start index of its basic block. /// MI is not required to have an index. SlotIndex getIndexBefore(const MachineInstr *MI) const { const MachineBasicBlock *MBB = MI->getParent(); -- cgit v1.1 From f4341e4155e272ec7e72ff61e100bafb50fc8bd8 Mon Sep 17 00:00:00 2001 From: Nadav Rotem Date: Mon, 23 Jul 2012 09:04:00 +0000 Subject: Doxygenify the comments of ISD nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160623 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/ISDOpcodes.h | 585 +++++++++++++++++++------------------- 1 file changed, 293 insertions(+), 292 deletions(-) (limited to 'include/llvm/CodeGen') diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index 3a92e9a..83a848c 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -37,87 +37,87 @@ namespace ISD { /// and getMachineOpcode() member functions of SDNode. /// enum NodeType { - // DELETED_NODE - This is an illegal value that is used to catch - // errors. This opcode is not a legal opcode for any node. + /// DELETED_NODE - This is an illegal value that is used to catch + /// errors. This opcode is not a legal opcode for any node. DELETED_NODE, - // EntryToken - This is the marker used to indicate the start of the region. + /// EntryToken - This is the marker used to indicate the start of a region. EntryToken, - // TokenFactor - This node takes multiple tokens as input and produces a - // single token result. This is used to represent the fact that the operand - // operators are independent of each other. + /// TokenFactor - This node takes multiple tokens as input and produces a + /// single token result. This is used to represent the fact that the operand + /// operators are independent of each other. TokenFactor, - // AssertSext, AssertZext - These nodes record if a register contains a - // value that has already been zero or sign extended from a narrower type. - // These nodes take two operands. The first is the node that has already - // been extended, and the second is a value type node indicating the width - // of the extension + /// AssertSext, AssertZext - These nodes record if a register contains a + /// value that has already been zero or sign extended from a narrower type. + /// These nodes take two operands. The first is the node that has already + /// been extended, and the second is a value type node indicating the width + /// of the extension AssertSext, AssertZext, - // Various leaf nodes. + /// Various leaf nodes. BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, Constant, ConstantFP, GlobalAddress, GlobalTLSAddress, FrameIndex, JumpTable, ConstantPool, ExternalSymbol, BlockAddress, - // The address of the GOT + /// The address of the GOT GLOBAL_OFFSET_TABLE, - // FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and - // llvm.returnaddress on the DAG. These nodes take one operand, the index - // of the frame or return address to return. An index of zero corresponds - // to the current function's frame or return address, an index of one to the - // parent's frame or return address, and so on. + /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and + /// llvm.returnaddress on the DAG. These nodes take one operand, the index + /// of the frame or return address to return. An index of zero corresponds + /// to the current function's frame or return address, an index of one to + /// the parent's frame or return address, and so on. FRAMEADDR, RETURNADDR, - // FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to - // first (possible) on-stack argument. This is needed for correct stack - // adjustment during unwind. + /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to + /// first (possible) on-stack argument. This is needed for correct stack + /// adjustment during unwind. FRAME_TO_ARGS_OFFSET, - // RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the - // address of the exception block on entry to an landing pad block. + /// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents the + /// address of the exception block on entry to an landing pad block. EXCEPTIONADDR, - // RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the - // address of the Language Specific Data Area for the enclosing function. + /// RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the + /// address of the Language Specific Data Area for the enclosing function. LSDAADDR, - // RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node represents - // the selection index of the exception thrown. + /// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node + /// represents the selection index of the exception thrown. EHSELECTION, - // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents - // 'eh_return' gcc dwarf builtin, which is used to return from - // exception. The general meaning is: adjust stack by OFFSET and pass - // execution to HANDLER. Many platform-related details also :) + /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents + /// 'eh_return' gcc dwarf builtin, which is used to return from + /// exception. The general meaning is: adjust stack by OFFSET and pass + /// execution to HANDLER. Many platform-related details also :) EH_RETURN, - // RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) - // This corresponds to the eh.sjlj.setjmp intrinsic. - // It takes an input chain and a pointer to the jump buffer as inputs - // and returns an outchain. + /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) + /// This corresponds to the eh.sjlj.setjmp intrinsic. + /// It takes an input chain and a pointer to the jump buffer as inputs + /// and returns an outchain. EH_SJLJ_SETJMP, - // OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) - // This corresponds to the eh.sjlj.longjmp intrinsic. - // It takes an input chain and a pointer to the jump buffer as inputs - // and returns an outchain. + /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) + /// This corresponds to the eh.sjlj.longjmp intrinsic. + /// It takes an input chain and a pointer to the jump buffer as inputs + /// and returns an outchain. EH_SJLJ_LONGJMP, - // TargetConstant* - Like Constant*, but the DAG does not do any folding, - // simplification, or lowering of the constant. They are used for constants - // which are known to fit in the immediate fields of their users, or for - // carrying magic numbers which are not values which need to be materialized - // in registers. + /// TargetConstant* - Like Constant*, but the DAG does not do any folding, + /// simplification, or lowering of the constant. They are used for constants + /// which are known to fit in the immediate fields of their users, or for + /// carrying magic numbers which are not values which need to be + /// materialized in registers. TargetConstant, TargetConstantFP, - // TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or - // anything else with this node, and this is valid in the target-specific - // dag, turning into a GlobalAddress operand. + /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or + /// anything else with this node, and this is valid in the target-specific + /// dag, turning into a GlobalAddress operand. TargetGlobalAddress, TargetGlobalTLSAddress, TargetFrameIndex, @@ -148,93 +148,94 @@ namespace ISD { /// namespace. The operands to the intrinsic follow. INTRINSIC_VOID, - // CopyToReg - This node has three operands: a chain, a register number to - // set to this value, and a value. + /// CopyToReg - This node has three operands: a chain, a register number to + /// set to this value, and a value. CopyToReg, - // CopyFromReg - This node indicates that the input value is a virtual or - // physical register that is defined outside of the scope of this - // SelectionDAG. The register is available from the RegisterSDNode object. + /// CopyFromReg - This node indicates that the input value is a virtual or + /// physical register that is defined outside of the scope of this + /// SelectionDAG. The register is available from the RegisterSDNode object. CopyFromReg, - // UNDEF - An undefined node + /// UNDEF - An undefined node. UNDEF, - // EXTRACT_ELEMENT - This is used to get the lower or upper (determined by - // a Constant, which is required to be operand #1) half of the integer or - // float value specified as operand #0. This is only for use before - // legalization, for values that will be broken into multiple registers. + /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by + /// a Constant, which is required to be operand #1) half of the integer or + /// float value specified as operand #0. This is only for use before + /// legalization, for values that will be broken into multiple registers. EXTRACT_ELEMENT, - // BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. Given - // two values of the same integer value type, this produces a value twice as - // big. Like EXTRACT_ELEMENT, this can only be used before legalization. + /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. + /// Given two values of the same integer value type, this produces a value + /// twice as big. Like EXTRACT_ELEMENT, this can only be used before + /// legalization. BUILD_PAIR, - // MERGE_VALUES - This node takes multiple discrete operands and returns - // them all as its individual results. This nodes has exactly the same - // number of inputs and outputs. This node is useful for some pieces of the - // code generator that want to think about a single node with multiple - // results, not multiple nodes. + /// MERGE_VALUES - This node takes multiple discrete operands and returns + /// them all as its individual results. This nodes has exactly the same + /// number of inputs and outputs. This node is useful for some pieces of the + /// code generator that want to think about a single node with multiple + /// results, not multiple nodes. MERGE_VALUES, - // Simple integer binary arithmetic operators. + /// Simple integer binary arithmetic operators. ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, - // SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing - // a signed/unsigned value of type i[2*N], and return the full value as - // two results, each of type iN. + /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing + /// a signed/unsigned value of type i[2*N], and return the full value as + /// two results, each of type iN. SMUL_LOHI, UMUL_LOHI, - // SDIVREM/UDIVREM - Divide two integers and produce both a quotient and - // remainder result. + /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and + /// remainder result. SDIVREM, UDIVREM, - // CARRY_FALSE - This node is used when folding other nodes, - // like ADDC/SUBC, which indicate the carry result is always false. + /// CARRY_FALSE - This node is used when folding other nodes, + /// like ADDC/SUBC, which indicate the carry result is always false. CARRY_FALSE, - // Carry-setting nodes for multiple precision addition and subtraction. - // These nodes take two operands of the same value type, and produce two - // results. The first result is the normal add or sub result, the second - // result is the carry flag result. + /// Carry-setting nodes for multiple precision addition and subtraction. + /// These nodes take two operands of the same value type, and produce two + /// results. The first result is the normal add or sub result, the second + /// result is the carry flag result. ADDC, SUBC, - // Carry-using nodes for multiple precision addition and subtraction. These - // nodes take three operands: The first two are the normal lhs and rhs to - // the add or sub, and the third is the input carry flag. These nodes - // produce two results; the normal result of the add or sub, and the output - // carry flag. These nodes both read and write a carry flag to allow them - // to them to be chained together for add and sub of arbitrarily large - // values. + /// Carry-using nodes for multiple precision addition and subtraction. These + /// nodes take three operands: The first two are the normal lhs and rhs to + /// the add or sub, and the third is the input carry flag. These nodes + /// produce two results; the normal result of the add or sub, and the output + /// carry flag. These nodes both read and write a carry flag to allow them + /// to them to be chained together for add and sub of arbitrarily large + /// values. ADDE, SUBE, - // RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. - // These nodes take two operands: the normal LHS and RHS to the add. They - // produce two results: the normal result of the add, and a boolean that - // indicates if an overflow occurred (*not* a flag, because it may be stored - // to memory, etc.). If the type of the boolean is not i1 then the high - // bits conform to getBooleanContents. - // These nodes are generated from the llvm.[su]add.with.overflow intrinsics. + /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. + /// These nodes take two operands: the normal LHS and RHS to the add. They + /// produce two results: the normal result of the add, and a boolean that + /// indicates if an overflow occurred (*not* a flag, because it may be store + /// to memory, etc.). If the type of the boolean is not i1 then the high + /// bits conform to getBooleanContents. + /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. SADDO, UADDO, - // Same for subtraction + /// Same for subtraction. SSUBO, USUBO, - // Same for multiplication + /// Same for multiplication. SMULO, UMULO, - // Simple binary floating point operators. + /// Simple binary floating point operators. FADD, FSUB, FMUL, FMA, FDIV, FREM, - // FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This - // DAG node does not require that X and Y have the same type, just that they - // are both floating point. X and the result must have the same type. - // FCOPYSIGN(f32, f64) is allowed. + /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This + /// DAG node does not require that X and Y have the same type, just that the + /// are both floating point. X and the result must have the same type. + /// FCOPYSIGN(f32, f64) is allowed. FCOPYSIGN, - // INT = FGETSIGN(FP) - Return the sign bit of the specified floating point - // value as an integer 0/1 value. + /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point + /// value as an integer 0/1 value. FGETSIGN, /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the @@ -292,13 +293,14 @@ namespace ISD { /// than the vector element type, and is implicitly truncated to it. SCALAR_TO_VECTOR, - // MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing - // an unsigned/signed value of type i[2*N], then return the top part. + /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, + /// producing an unsigned/signed value of type i[2*N], then return the top + /// part. MULHU, MULHS, /// Bitwise operators - logical and, logical or, logical xor. AND, OR, XOR, - + /// Shift and rotation operations. After legalization, the type of the /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization /// the shift amount can be any type, but care must be taken to ensure it is @@ -306,7 +308,6 @@ namespace ISD { /// legalization, types like i1024 can occur and i8 doesn't have enough bits /// to represent the shift amount. By convention, DAGCombine and /// SelectionDAGBuilder forces these shift amounts to i32 for simplicity. - /// SHL, SRA, SRL, ROTL, ROTR, /// Byte Swap and Counting operators. @@ -315,67 +316,67 @@ namespace ISD { /// Bit counting operators with an undefined result for zero inputs. CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, - // Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not - // i1 then the high bits must conform to getBooleanContents. + /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not + /// i1 then the high bits must conform to getBooleanContents. SELECT, - // Select with a vector condition (op #0) and two vector operands (ops #1 - // and #2), returning a vector result. All vectors have the same length. - // Much like the scalar select and setcc, each bit in the condition selects - // whether the corresponding result element is taken from op #1 or op #2. - // At first, the VSELECT condition is of vXi1 type. Later, targets may change - // the condition type in order to match the VSELECT node using a a pattern. - // The condition follows the BooleanContent format of the target. + /// Select with a vector condition (op #0) and two vector operands (ops #1 + /// and #2), returning a vector result. All vectors have the same length. + /// Much like the scalar select and setcc, each bit in the condition selects + /// whether the corresponding result element is taken from op #1 or op #2. + /// At first, the VSELECT condition is of vXi1 type. Later, targets may + /// change the condition type in order to match the VSELECT node using a + /// pattern. The condition follows the BooleanContent format of the target. VSELECT, - // Select with condition operator - This selects between a true value and - // a false value (ops #2 and #3) based on the boolean result of comparing - // the lhs and rhs (ops #0 and #1) of a conditional expression with the - // condition code in op #4, a CondCodeSDNode. + /// Select with condition operator - This selects between a true value and + /// a false value (ops #2 and #3) based on the boolean result of comparing + /// the lhs and rhs (ops #0 and #1) of a conditional expression with the + /// condition code in op #4, a CondCodeSDNode. SELECT_CC, - // SetCC operator - This evaluates to a true value iff the condition is - // true. If the result value type is not i1 then the high bits conform - // to getBooleanContents. The operands to this are the left and right - // operands to compare (ops #0, and #1) and the condition code to compare - // them with (op #2) as a CondCodeSDNode. If the operands are vector types - // then the result type must also be a vector type. + /// SetCC operator - This evaluates to a true value iff the condition is + /// true. If the result value type is not i1 then the high bits conform + /// to getBooleanContents. The operands to this are the left and right + /// operands to compare (ops #0, and #1) and the condition code to compare + /// them with (op #2) as a CondCodeSDNode. If the operands are vector types + /// then the result type must also be a vector type. SETCC, - // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded - // integer shift operations, just like ADD/SUB_PARTS. The operation - // ordering is: - // [Lo,Hi] = op [LoLHS,HiLHS], Amt + /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded + /// integer shift operations, just like ADD/SUB_PARTS. The operation + /// ordering is: + /// [Lo,Hi] = op [LoLHS,HiLHS], Amt SHL_PARTS, SRA_PARTS, SRL_PARTS, - // Conversion operators. These are all single input single output - // operations. For all of these, the result type must be strictly - // wider or narrower (depending on the operation) than the source - // type. + /// Conversion operators. These are all single input single output + /// operations. For all of these, the result type must be strictly + /// wider or narrower (depending on the operation) than the source + /// type. - // SIGN_EXTEND - Used for integer types, replicating the sign bit - // into new bits. + /// SIGN_EXTEND - Used for integer types, replicating the sign bit + /// into new bits. SIGN_EXTEND, - // ZERO_EXTEND - Used for integer types, zeroing the new bits. + /// ZERO_EXTEND - Used for integer types, zeroing the new bits. ZERO_EXTEND, - // ANY_EXTEND - Used for integer types. The high bits are undefined. + /// ANY_EXTEND - Used for integer types. The high bits are undefined. ANY_EXTEND, - // TRUNCATE - Completely drop the high bits. + /// TRUNCATE - Completely drop the high bits. TRUNCATE, - // [SU]INT_TO_FP - These operators convert integers (whose interpreted sign - // depends on the first letter) to floating point. + /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign + /// depends on the first letter) to floating point. SINT_TO_FP, UINT_TO_FP, - // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to - // sign extend a small value in a large integer register (e.g. sign - // extending the low 8 bits of a 32-bit register to fill the top 24 bits - // with the 7th bit). The size of the smaller type is indicated by the 1th - // operand, a ValueType node. + /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to + /// sign extend a small value in a large integer register (e.g. sign + /// extending the low 8 bits of a 32-bit register to fill the top 24 bits + /// with the 7th bit). The size of the smaller type is indicated by the 1th + /// operand, a ValueType node. SIGN_EXTEND_INREG, /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned @@ -396,12 +397,12 @@ namespace ISD { /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. FP_ROUND, - // FLT_ROUNDS_ - Returns current rounding mode: - // -1 Undefined - // 0 Round to 0 - // 1 Round to nearest - // 2 Round to +inf - // 3 Round to -inf + /// FLT_ROUNDS_ - Returns current rounding mode: + /// -1 Undefined + /// 0 Round to 0 + /// 1 Round to nearest + /// 2 Round to +inf + /// 3 Round to -inf FLT_ROUNDS_, /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and @@ -414,211 +415,211 @@ namespace ISD { /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. FP_EXTEND, - // BITCAST - This operator converts between integer, vector and FP - // values, as if the value was stored to memory with one type and loaded - // from the same address with the other type (or equivalently for vector - // format conversions, etc). The source and result are required to have - // the same bit size (e.g. f32 <-> i32). This can also be used for - // int-to-int or fp-to-fp conversions, but that is a noop, deleted by - // getNode(). + /// BITCAST - This operator converts between integer, vector and FP + /// values, as if the value was stored to memory with one type and loaded + /// from the same address with the other type (or equivalently for vector + /// format conversions, etc). The source and result are required to have + /// the same bit size (e.g. f32 <-> i32). This can also be used for + /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by + /// getNode(). BITCAST, - // CONVERT_RNDSAT - This operator is used to support various conversions - // between various types (float, signed, unsigned and vectors of those - // types) with rounding and saturation. NOTE: Avoid using this operator as - // most target don't support it and the operator might be removed in the - // future. It takes the following arguments: - // 0) value - // 1) dest type (type to convert to) - // 2) src type (type to convert from) - // 3) rounding imm - // 4) saturation imm - // 5) ISD::CvtCode indicating the type of conversion to do + /// CONVERT_RNDSAT - This operator is used to support various conversions + /// between various types (float, signed, unsigned and vectors of those + /// types) with rounding and saturation. NOTE: Avoid using this operator as + /// most target don't support it and the operator might be removed in the + /// future. It takes the following arguments: + /// 0) value + /// 1) dest type (type to convert to) + /// 2) src type (type to convert from) + /// 3) rounding imm + /// 4) saturation imm + /// 5) ISD::CvtCode indicating the type of conversion to do CONVERT_RNDSAT, - // FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform - // promotions and truncation for half-precision (16 bit) floating - // numbers. We need special nodes since FP16 is a storage-only type with - // special semantics of operations. + /// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform + /// promotions and truncation for half-precision (16 bit) floating + /// numbers. We need special nodes since FP16 is a storage-only type with + /// special semantics of operations. FP16_TO_FP32, FP32_TO_FP16, - // FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, - // FLOG, FLOG2, FLOG10, FEXP, FEXP2, - // FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary floating - // point operations. These are inspired by libm. + /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, + /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, + /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary + /// floating point operations. These are inspired by libm. FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2, FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, - // LOAD and STORE have token chains as their first operand, then the same - // operands as an LLVM load/store instruction, then an offset node that - // is added / subtracted from the base pointer to form the address (for - // indexed memory ops). + /// LOAD and STORE have token chains as their first operand, then the same + /// operands as an LLVM load/store instruction, then an offset node that + /// is added / subtracted from the base pointer to form the address (for + /// indexed memory ops). LOAD, STORE, - // DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned - // to a specified boundary. This node always has two return values: a new - // stack pointer value and a chain. The first operand is the token chain, - // the second is the number of bytes to allocate, and the third is the - // alignment boundary. The size is guaranteed to be a multiple of the stack - // alignment, and the alignment is guaranteed to be bigger than the stack - // alignment (if required) or 0 to get standard stack alignment. + /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned + /// to a specified boundary. This node always has two return values: a new + /// stack pointer value and a chain. The first operand is the token chain, + /// the second is the number of bytes to allocate, and the third is the + /// alignment boundary. The size is guaranteed to be a multiple of the + /// stack alignment, and the alignment is guaranteed to be bigger than the + /// stack alignment (if required) or 0 to get standard stack alignment. DYNAMIC_STACKALLOC, - // Control flow instructions. These all have token chains. + /// Control flow instructions. These all have token chains. - // BR - Unconditional branch. The first operand is the chain - // operand, the second is the MBB to branch to. + /// BR - Unconditional branch. The first operand is the chain + /// operand, the second is the MBB to branch to. BR, - // BRIND - Indirect branch. The first operand is the chain, the second - // is the value to branch to, which must be of the same type as the target's - // pointer type. + /// BRIND - Indirect branch. The first operand is the chain, the second + /// is the value to branch to, which must be of the same type as the + /// target's pointer type. BRIND, - // BR_JT - Jumptable branch. The first operand is the chain, the second - // is the jumptable index, the last one is the jumptable entry index. + /// BR_JT - Jumptable branch. The first operand is the chain, the second + /// is the jumptable index, the last one is the jumptable entry index. BR_JT, - // BRCOND - Conditional branch. The first operand is the chain, the - // second is the condition, the third is the block to branch to if the - // condition is true. If the type of the condition is not i1, then the - // high bits must conform to getBooleanContents. + /// BRCOND - Conditional branch. The first operand is the chain, the + /// second is the condition, the third is the block to branch to if the + /// condition is true. If the type of the condition is not i1, then the + /// high bits must conform to getBooleanContents. BRCOND, - // BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in - // that the condition is represented as condition code, and two nodes to - // compare, rather than as a combined SetCC node. The operands in order are - // chain, cc, lhs, rhs, block to branch to if condition is true. + /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in + /// that the condition is represented as condition code, and two nodes to + /// compare, rather than as a combined SetCC node. The operands in order + /// are chain, cc, lhs, rhs, block to branch to if condition is true. BR_CC, - // INLINEASM - Represents an inline asm block. This node always has two - // return values: a chain and a flag result. The inputs are as follows: - // Operand #0 : Input chain. - // Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. - // Operand #2 : a MDNodeSDNode with the !srcloc metadata. - // Operand #3 : HasSideEffect, IsAlignStack bits. - // After this, it is followed by a list of operands with this format: - // ConstantSDNode: Flags that encode whether it is a mem or not, the - // of operands that follow, etc. See InlineAsm.h. - // ... however many operands ... - // Operand #last: Optional, an incoming flag. - // - // The variable width operands are required to represent target addressing - // modes as a single "operand", even though they may have multiple - // SDOperands. + /// INLINEASM - Represents an inline asm block. This node always has two + /// return values: a chain and a flag result. The inputs are as follows: + /// Operand #0 : Input chain. + /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. + /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. + /// Operand #3 : HasSideEffect, IsAlignStack bits. + /// After this, it is followed by a list of operands with this format: + /// ConstantSDNode: Flags that encode whether it is a mem or not, the + /// of operands that follow, etc. See InlineAsm.h. + /// ... however many operands ... + /// Operand #last: Optional, an incoming flag. + /// + /// The variable width operands are required to represent target addressing + /// modes as a single "operand", even though they may have multiple + /// SDOperands. INLINEASM, - // EH_LABEL - Represents a label in mid basic block used to track - // locations needed for debug and exception handling tables. These nodes - // take a chain as input and return a chain. + /// EH_LABEL - Represents a label in mid basic block used to track + /// locations needed for debug and exception handling tables. These nodes + /// take a chain as input and return a chain. EH_LABEL, - // STACKSAVE - STACKSAVE has one operand, an input chain. It produces a - // value, the same type as the pointer type for the system, and an output - // chain. + /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a + /// value, the same type as the pointer type for the system, and an output + /// chain. STACKSAVE, - // STACKRESTORE has two operands, an input chain and a pointer to restore to - // it returns an output chain. + /// STACKRESTORE has two operands, an input chain and a pointer to restore + /// to it returns an output chain. STACKRESTORE, - // CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of - // a call sequence, and carry arbitrary information that target might want - // to know. The first operand is a chain, the rest are specified by the - // target and not touched by the DAG optimizers. - // CALLSEQ_START..CALLSEQ_END pairs may not be nested. + /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end + /// of a call sequence, and carry arbitrary information that target might + /// want to know. The first operand is a chain, the rest are specified by + /// the target and not touched by the DAG optimizers. + /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. CALLSEQ_START, // Beginning of a call sequence CALLSEQ_END, // End of a call sequence - // VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, - // and the alignment. It returns a pair of values: the vaarg value and a - // new chain. + /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, + /// and the alignment. It returns a pair of values: the vaarg value and a + /// new chain. VAARG, - // VACOPY - VACOPY has five operands: an input chain, a destination pointer, - // a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the - // source. + /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, + /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the + /// source. VACOPY, - // VAEND, VASTART - VAEND and VASTART have three operands: an input chain, a - // pointer, and a SRCVALUE. + /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, + /// pointer, and a SRCVALUE. VAEND, VASTART, - // SRCVALUE - This is a node type that holds a Value* that is used to - // make reference to a value in the LLVM IR. + /// SRCVALUE - This is a node type that holds a Value* that is used to + /// make reference to a value in the LLVM IR. SRCVALUE, - // MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to - // reference metadata in the IR. + /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to + /// reference metadata in the IR. MDNODE_SDNODE, - // PCMARKER - This corresponds to the pcmarker intrinsic. + /// PCMARKER - This corresponds to the pcmarker intrinsic. PCMARKER, - // READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. - // The only operand is a chain and a value and a chain are produced. The - // value is the contents of the architecture specific cycle counter like - // register (or other high accuracy low latency clock source) + /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. + /// The only operand is a chain and a value and a chain are produced. The + /// value is the contents of the architecture specific cycle counter like + /// register (or other high accuracy low latency clock source) READCYCLECOUNTER, - // HANDLENODE node - Used as a handle for various purposes. + /// HANDLENODE node - Used as a handle for various purposes. HANDLENODE, - // INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It - // takes as input a token chain, the pointer to the trampoline, the pointer - // to the nested function, the pointer to pass for the 'nest' parameter, a - // SRCVALUE for the trampoline and another for the nested function (allowing - // targets to access the original Function*). It produces a token chain as - // output. + /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It + /// takes as input a token chain, the pointer to the trampoline, the pointer + /// to the nested function, the pointer to pass for the 'nest' parameter, a + /// SRCVALUE for the trampoline and another for the nested function + /// (allowing targets to access the original Function*). + /// It produces a token chain as output. INIT_TRAMPOLINE, - // ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. - // It takes a pointer to the trampoline and produces a (possibly) new - // pointer to the same trampoline with platform-specific adjustments - // applied. The pointer it returns points to an executable block of code. + /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. + /// It takes a pointer to the trampoline and produces a (possibly) new + /// pointer to the same trampoline with platform-specific adjustments + /// applied. The pointer it returns points to an executable block of code. ADJUST_TRAMPOLINE, - // TRAP - Trapping instruction + /// TRAP - Trapping instruction TRAP, - // DEBUGTRAP - Trap intended to get the attention of a debugger. + /// DEBUGTRAP - Trap intended to get the attention of a debugger. DEBUGTRAP, - // PREFETCH - This corresponds to a prefetch intrinsic. The first operand - // is the chain. The other operands are the address to prefetch, - // read / write specifier, locality specifier and instruction / data cache - // specifier. + /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand + /// is the chain. The other operands are the address to prefetch, + /// read / write specifier, locality specifier and instruction / data cache + /// specifier. PREFETCH, - // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, - // store-store, device) - // This corresponds to the memory.barrier intrinsic. - // it takes an input chain, 4 operands to specify the type of barrier, an - // operand specifying if the barrier applies to device and uncached memory - // and produces an output chain. + /// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load, + /// store-store, device) + /// This corresponds to the memory.barrier intrinsic. + /// it takes an input chain, 4 operands to specify the type of barrier, an + /// operand specifying if the barrier applies to device and uncached memory + /// and produces an output chain. MEMBARRIER, - // OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) - // This corresponds to the fence instruction. It takes an input chain, and - // two integer constants: an AtomicOrdering and a SynchronizationScope. + /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) + /// This corresponds to the fence instruction. It takes an input chain, and + /// two integer constants: an AtomicOrdering and a SynchronizationScope. ATOMIC_FENCE, - // Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) - // This corresponds to "load atomic" instruction. + /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) + /// This corresponds to "load atomic" instruction. ATOMIC_LOAD, - // OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) - // This corresponds to "store atomic" instruction. + /// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val) + /// This corresponds to "store atomic" instruction. ATOMIC_STORE, - // Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) - // This corresponds to the cmpxchg instruction. + /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) + /// This corresponds to the cmpxchg instruction. ATOMIC_CMP_SWAP, - // Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) - // Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) - // These correspond to the atomicrmw instruction. + /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) + /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) + /// These correspond to the atomicrmw instruction. ATOMIC_SWAP, ATOMIC_LOAD_ADD, ATOMIC_LOAD_SUB, @@ -793,16 +794,16 @@ namespace ISD { /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT /// supports. enum CvtCode { - CVT_FF, // Float from Float - CVT_FS, // Float from Signed - CVT_FU, // Float from Unsigned - CVT_SF, // Signed from Float - CVT_UF, // Unsigned from Float - CVT_SS, // Signed from Signed - CVT_SU, // Signed from Unsigned - CVT_US, // Unsigned from Signed - CVT_UU, // Unsigned from Unsigned - CVT_INVALID // Marker - Invalid opcode + CVT_FF, /// Float from Float + CVT_FS, /// Float from Signed + CVT_FU, /// Float from Unsigned + CVT_SF, /// Signed from Float + CVT_UF, /// Unsigned from Float + CVT_SS, /// Signed from Signed + CVT_SU, /// Signed from Unsigned + CVT_US, /// Unsigned from Signed + CVT_UU, /// Unsigned from Unsigned + CVT_INVALID /// Marker - Invalid opcode }; } // end llvm::ISD namespace -- cgit v1.1