From 36b56886974eae4f9c5ebc96befd3e7bfe5de338 Mon Sep 17 00:00:00 2001 From: Stephen Hines Date: Wed, 23 Apr 2014 16:57:46 -0700 Subject: Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617 --- include/llvm/IR/IntrinsicsARM.td | 90 ++++++++++++++++++++++------------------ 1 file changed, 50 insertions(+), 40 deletions(-) (limited to 'include/llvm/IR/IntrinsicsARM.td') diff --git a/include/llvm/IR/IntrinsicsARM.td b/include/llvm/IR/IntrinsicsARM.td index 0b50d64..482f98e 100644 --- a/include/llvm/IR/IntrinsicsARM.td +++ b/include/llvm/IR/IntrinsicsARM.td @@ -38,12 +38,20 @@ def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">, def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>; def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>; + +def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>; +def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>; + def int_arm_clrex : Intrinsic<[]>; def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>; def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>; +def int_arm_stlexd : Intrinsic<[llvm_i32_ty], + [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>; +def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>; + //===----------------------------------------------------------------------===// // Data barrier instructions def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>; @@ -123,20 +131,15 @@ def int_arm_sevl : Intrinsic<[], []>; class Neon_1Arg_Intrinsic : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; class Neon_1Arg_Narrow_Intrinsic - : Intrinsic<[llvm_anyvector_ty], - [LLVMExtendedElementVectorType<0>], [IntrNoMem]>; + : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>; class Neon_2Arg_Intrinsic : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; class Neon_2Arg_Narrow_Intrinsic - : Intrinsic<[llvm_anyvector_ty], - [LLVMExtendedElementVectorType<0>, - LLVMExtendedElementVectorType<0>], + : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>], [IntrNoMem]>; class Neon_2Arg_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], - [LLVMTruncatedElementVectorType<0>, - LLVMTruncatedElementVectorType<0>], + : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>], [IntrNoMem]>; class Neon_3Arg_Intrinsic : Intrinsic<[llvm_anyvector_ty], @@ -144,9 +147,7 @@ class Neon_3Arg_Intrinsic [IntrNoMem]>; class Neon_3Arg_Long_Intrinsic : Intrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, - LLVMTruncatedElementVectorType<0>, - LLVMTruncatedElementVectorType<0>], + [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>], [IntrNoMem]>; class Neon_CvtFxToFP_Intrinsic : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; @@ -155,6 +156,10 @@ class Neon_CvtFPToFx_Intrinsic class Neon_CvtFPtoInt_1Arg_Intrinsic : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; +class Neon_Compare_Intrinsic + : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], + [IntrNoMem]>; + // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors. // Besides the table, VTBL has one other v8i8 argument and VTBX has two. // Overall, the classes range from 2 to 6 v8i8 arguments. @@ -224,18 +229,8 @@ def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic; def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic; // Vector Absolute Compare. -def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty], - [llvm_v2f32_ty, llvm_v2f32_ty], - [IntrNoMem]>; -def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty], - [llvm_v4f32_ty, llvm_v4f32_ty], - [IntrNoMem]>; -def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty], - [llvm_v2f32_ty, llvm_v2f32_ty], - [IntrNoMem]>; -def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty], - [llvm_v4f32_ty, llvm_v4f32_ty], - [IntrNoMem]>; +def int_arm_neon_vacge : Neon_Compare_Intrinsic; +def int_arm_neon_vacgt : Neon_Compare_Intrinsic; // Vector Absolute Differences. def int_arm_neon_vabds : Neon_2Arg_Intrinsic; @@ -293,9 +288,6 @@ def int_arm_neon_vpminu : Neon_2Arg_Intrinsic; // Vector Shift. def int_arm_neon_vshifts : Neon_2Arg_Intrinsic; def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic; -def int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic; -def int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic; -def int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic; // Vector Rounding Shift. def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic; @@ -472,19 +464,37 @@ def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty], // Crypto instructions -def int_arm_neon_aesd : Neon_2Arg_Intrinsic; -def int_arm_neon_aese : Neon_2Arg_Intrinsic; -def int_arm_neon_aesimc : Neon_1Arg_Intrinsic; -def int_arm_neon_aesmc : Neon_1Arg_Intrinsic; -def int_arm_neon_sha1h : Neon_1Arg_Intrinsic; -def int_arm_neon_sha1su1 : Neon_2Arg_Intrinsic; -def int_arm_neon_sha256su0 : Neon_2Arg_Intrinsic; -def int_arm_neon_sha1c : Neon_3Arg_Intrinsic; -def int_arm_neon_sha1m : Neon_3Arg_Intrinsic; -def int_arm_neon_sha1p : Neon_3Arg_Intrinsic; -def int_arm_neon_sha1su0: Neon_3Arg_Intrinsic; -def int_arm_neon_sha256h: Neon_3Arg_Intrinsic; -def int_arm_neon_sha256h2: Neon_3Arg_Intrinsic; -def int_arm_neon_sha256su1: Neon_3Arg_Intrinsic; +class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty], + [llvm_v16i8_ty], [IntrNoMem]>; +class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty], + [llvm_v16i8_ty, llvm_v16i8_ty], + [IntrNoMem]>; + +class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem]>; +class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_v4i32_ty], + [IntrNoMem]>; +class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], + [IntrNoMem]>; +class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty], + [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty], + [IntrNoMem]>; + +def int_arm_neon_aesd : AES_2Arg_Intrinsic; +def int_arm_neon_aese : AES_2Arg_Intrinsic; +def int_arm_neon_aesimc : AES_1Arg_Intrinsic; +def int_arm_neon_aesmc : AES_1Arg_Intrinsic; +def int_arm_neon_sha1h : SHA_1Arg_Intrinsic; +def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic; +def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic; +def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic; +def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic; +def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic; +def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic; +def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic; +def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic; +def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic; } // end TargetPrefix -- cgit v1.1