From 9c130672761e006c47ea23b34a7bd414f2cd8368 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Tue, 4 Sep 2012 18:36:28 +0000 Subject: Allow tied uses and defs in different orders. After much agonizing, use a full 4 bits of precious MachineOperand space to encode this. This uses existing padding, and doesn't grow MachineOperand beyond its current 32 bytes. This allows tied defs among the first 15 operands on a normal instruction, just like the current MCInstrDesc constraint encoding. Inline assembly needs to be able to tie more than the first 15 operands, and gets special treatment. Tied uses can appear beyond 15 operands, as long as they are tied to a def that's in range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163151 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 4 ++-- include/llvm/CodeGen/MachineOperand.h | 17 +++++++---------- 2 files changed, 9 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 67ae3f9..e6ed56b 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -952,8 +952,8 @@ private: void untieRegOperand(unsigned OpIdx) { MachineOperand &MO = getOperand(OpIdx); if (MO.isReg() && MO.isTied()) { - getOperand(findTiedOperandIdx(OpIdx)).IsTied = false; - MO.IsTied = false; + getOperand(findTiedOperandIdx(OpIdx)).TiedTo = false; + MO.TiedTo = false; } } diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h index baec882..5c6662e 100644 --- a/include/llvm/CodeGen/MachineOperand.h +++ b/include/llvm/CodeGen/MachineOperand.h @@ -70,6 +70,11 @@ private: unsigned char TargetFlags; }; + /// TiedTo - Non-zero when this register operand is tied to another register + /// operand. The encoding of this field is described in the block comment + /// before MachineInstr::tieOperands(). + unsigned char TiedTo : 4; + /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register /// operands. @@ -124,14 +129,6 @@ private: /// model the GCC inline asm '&' constraint modifier. bool IsEarlyClobber : 1; - /// IsTied - True if this MO_Register operand is tied to another operand on - /// the instruction. Tied operands form def-use pairs that must be assigned - /// the same physical register by the register allocator, but they will have - /// different virtual registers while the code is in SSA form. - /// - /// See MachineInstr::isRegTiedToUseOperand() and isRegTiedToDefOperand(). - bool IsTied : 1; - /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, /// not a real instruction. Such uses should be ignored during codegen. bool IsDebug : 1; @@ -309,7 +306,7 @@ public: bool isTied() const { assert(isReg() && "Wrong MachineOperand accessor"); - return IsTied; + return TiedTo; } bool isDebug() const { @@ -572,7 +569,7 @@ public: Op.IsUndef = isUndef; Op.IsInternalRead = isInternalRead; Op.IsEarlyClobber = isEarlyClobber; - Op.IsTied = false; + Op.TiedTo = 0; Op.IsDebug = isDebug; Op.SmallContents.RegNo = Reg; Op.Contents.Reg.Prev = 0; -- cgit v1.1