From c9403659a98bf6487ab6fbf40b81628b5695c02e Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Wed, 7 Jul 2010 15:54:55 +0000
Subject: Split the SDValue out of OutputArg so that SelectionDAG-independent
 code can do calling-convention queries. This obviates OutputArgReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/CallingConvLower.h |  4 ----
 include/llvm/Target/TargetCallingConv.h | 29 +++++------------------------
 include/llvm/Target/TargetLowering.h    |  2 ++
 3 files changed, 7 insertions(+), 28 deletions(-)

(limited to 'include')

diff --git a/include/llvm/CodeGen/CallingConvLower.h b/include/llvm/CodeGen/CallingConvLower.h
index 7c6140f..5ce59b8 100644
--- a/include/llvm/CodeGen/CallingConvLower.h
+++ b/include/llvm/CodeGen/CallingConvLower.h
@@ -184,8 +184,6 @@ public:
   /// incorporating info about the result values into this state.
   void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
                      CCAssignFn Fn);
-  void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
-                     CCAssignFn Fn);
 
   /// CheckReturn - Analyze the return values of a function, returning
   /// true if the return can be performed without sret-demotion, and
@@ -198,8 +196,6 @@ public:
   /// incorporating info about the passed values into this state.
   void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
                            CCAssignFn Fn);
-  void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
-                           CCAssignFn Fn);
 
   /// AnalyzeCallOperands - Same as above except it takes vectors of types
   /// and argument flags.
diff --git a/include/llvm/Target/TargetCallingConv.h b/include/llvm/Target/TargetCallingConv.h
index 0c7147e..f368a2e 100644
--- a/include/llvm/Target/TargetCallingConv.h
+++ b/include/llvm/Target/TargetCallingConv.h
@@ -14,8 +14,6 @@
 #ifndef LLVM_TARGET_TARGETCALLINGCONV_H
 #define LLVM_TARGET_TARGETCALLINGCONV_H
 
-#include "llvm/CodeGen/SelectionDAGNodes.h"
-
 namespace llvm {
 
 namespace ISD {
@@ -112,7 +110,7 @@ namespace ISD {
     bool Used;
 
     InputArg() : VT(MVT::Other), Used(false) {}
-    InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
+    InputArg(ArgFlagsTy flags, EVT vt, bool used)
       : Flags(flags), VT(vt), Used(used) {
       assert(VT.isSimple() &&
              "InputArg value type must be Simple!");
@@ -125,35 +123,18 @@ namespace ISD {
   ///
   struct OutputArg {
     ArgFlagsTy Flags;
-    SDValue Val;
+    EVT VT;
 
     /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
     bool IsFixed;
 
     OutputArg() : IsFixed(false) {}
-    OutputArg(ISD::ArgFlagsTy flags, SDValue val, bool isfixed)
-      : Flags(flags), Val(val), IsFixed(isfixed) {
-      assert(Val.getValueType().isSimple() &&
+    OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed)
+      : Flags(flags), VT(vt), IsFixed(isfixed) {
+      assert(VT.isSimple() &&
              "OutputArg value type must be Simple!");
     }
   };
-
-  /// OutputArgReg - This struct carries flags and a register value for a
-  /// single outgoing (actual) argument or outgoing (from the perspective
-  /// of the caller) return value virtual register.
-  ///
-  struct OutputArgReg {
-    ArgFlagsTy Flags;
-    EVT VT;
-    unsigned Reg;
-
-    /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
-    bool IsFixed;
-
-    OutputArgReg() : IsFixed(false) {}
-    OutputArgReg(ISD::ArgFlagsTy flags, EVT vt, unsigned reg, bool isfixed)
-      : Flags(flags), VT(vt), Reg(reg), IsFixed(isfixed) {}
-  };
 }
 
 } // end llvm namespace
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 449bb68..230f7fa 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -1145,6 +1145,7 @@ public:
     LowerCall(SDValue Chain, SDValue Callee,
               CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
               const SmallVectorImpl<ISD::OutputArg> &Outs,
+              const SmallVectorImpl<SDValue> &OutVals,
               const SmallVectorImpl<ISD::InputArg> &Ins,
               DebugLoc dl, SelectionDAG &DAG,
               SmallVectorImpl<SDValue> &InVals) const {
@@ -1173,6 +1174,7 @@ public:
   virtual SDValue
     LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                 const SmallVectorImpl<ISD::OutputArg> &Outs,
+                const SmallVectorImpl<SDValue> &OutVals,
                 DebugLoc dl, SelectionDAG &DAG) const {
     assert(0 && "Not Implemented");
     return SDValue();    // this is here to silence compiler errors
-- 
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