From f17a25c88b892d30c2b41ba7ecdfbdfb2b4be9cc Mon Sep 17 00:00:00 2001
From: Dan Gohman <djg@cray.com>
Date: Wed, 18 Jul 2007 16:29:46 +0000
Subject: It's not necessary to do rounding for alloca operations when the
 requested alignment is equal to the stack alignment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40004 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/PostRASchedulerList.cpp | 81 +++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 lib/CodeGen/PostRASchedulerList.cpp

(limited to 'lib/CodeGen/PostRASchedulerList.cpp')

diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp
new file mode 100644
index 0000000..06f47c7
--- /dev/null
+++ b/lib/CodeGen/PostRASchedulerList.cpp
@@ -0,0 +1,81 @@
+//===----- SchedulePostRAList.cpp - list scheduler ------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Dale Johannesen and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This implements a top-down list scheduler, using standard algorithms.
+// The basic approach uses a priority queue of available nodes to schedule.
+// One at a time, nodes are taken from the priority queue (thus in priority
+// order), checked for legality to schedule, and emitted if legal.
+//
+// Nodes may not be legal to schedule either due to structural hazards (e.g.
+// pipeline or resource constraints) or because an input to the instruction has
+// not completed execution.
+//
+//===----------------------------------------------------------------------===//
+
+#define DEBUG_TYPE "post-RA-sched"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/Support/Debug.h"
+//#include "llvm/ADT/Statistic.h"
+//#include <climits>
+//#include <queue>
+#include "llvm/Support/CommandLine.h"
+using namespace llvm;
+
+namespace {
+  bool NoPostRAScheduling;
+
+  // When this works it will be on by default.
+  cl::opt<bool, true>
+  DisablePostRAScheduler("disable-post-RA-scheduler",
+               cl::desc("Disable scheduling after register allocation"),
+               cl::location(NoPostRAScheduling),
+               cl::init(true));
+
+  class VISIBILITY_HIDDEN SchedulePostRATDList : public MachineFunctionPass {
+  public:
+    static char ID;
+    SchedulePostRATDList() : MachineFunctionPass((intptr_t)&ID) {}
+  private:
+    MachineFunction *MF;
+    const TargetMachine *TM;
+  public:
+    const char *getPassName() const {
+      return "Post RA top-down list latency scheduler (STUB)";
+    }
+
+    bool runOnMachineFunction(MachineFunction &Fn);
+  };
+  char SchedulePostRATDList::ID = 0;
+}
+
+bool SchedulePostRATDList::runOnMachineFunction(MachineFunction &Fn) {
+  if (NoPostRAScheduling)
+    return true;
+
+  DOUT << "SchedulePostRATDList\n";
+  MF = &Fn;
+  TM = &MF->getTarget();
+
+  // Loop over all of the basic blocks
+  for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
+       MBB != MBBe; ++MBB)
+    ;
+
+  return true;
+}
+  
+
+//===----------------------------------------------------------------------===//
+//                         Public Constructor Functions
+//===----------------------------------------------------------------------===//
+
+FunctionPass *llvm::createPostRAScheduler() {
+  return new SchedulePostRATDList();
+}
-- 
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