From 1c2f6da3319ed97f5a0927970f656295c0c22632 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 29 Apr 2009 00:42:27 +0000 Subject: Determine allocation 'preference' with right register class. I haven't seen this changing codegen so no test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70351 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/RegAllocLinearScan.cpp | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'lib/CodeGen/RegAllocLinearScan.cpp') diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 2e65b3f..2ed902c 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -799,8 +799,14 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) Reg = SrcReg; else if (vrm_->isAssignedReg(SrcReg)) Reg = vrm_->getPhys(SrcReg); - if (Reg && allocatableRegs_[Reg] && RC->contains(Reg)) - cur->preference = Reg; + if (Reg) { + if (SrcSubReg) + Reg = tri_->getSubReg(Reg, SrcSubReg); + if (DstSubReg) + Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC); + if (Reg && allocatableRegs_[Reg] && RC->contains(Reg)) + cur->preference = Reg; + } } } } @@ -1265,14 +1271,10 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { // If copy coalescer has assigned a "preferred" register, check if it's // available first. if (cur->preference) { + DOUT << "(preferred: " << tri_->getName(cur->preference) << ") "; if (prt_->isRegAvail(cur->preference) && - RC->contains(cur->preference)) { - DOUT << "\t\tassigned the preferred register: " - << tri_->getName(cur->preference) << "\n"; + RC->contains(cur->preference)) return cur->preference; - } else - DOUT << "\t\tunable to assign the preferred register: " - << tri_->getName(cur->preference) << "\n"; } if (!DowngradedRegs.empty()) { -- cgit v1.1