From 4dc478308f0de13d9ce20915193ac8c3318c5bd6 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 12 Jan 2013 19:06:44 +0000 Subject: When lowering an inreg sext first shift left, then right arithmetically. Shifting right two times will only yield zero. Should fix SingleSource/UnitTests/SignlessTypes/factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp') diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 2dade85..3989295 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -508,9 +508,9 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) { SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) { EVT VT = Op.getValueType(); - // Make sure that the SRA and SRL instructions are available. + // Make sure that the SRA and SHL instructions are available. if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand || - TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) + TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand) return DAG.UnrollVectorOp(Op.getNode()); DebugLoc DL = Op.getDebugLoc(); @@ -521,7 +521,7 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) { SDValue ShiftSz = DAG.getConstant(BW - OrigBW, VT); Op = Op.getOperand(0); - Op = DAG.getNode(ISD::SRL, DL, VT, Op, ShiftSz); + Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz); return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz); } -- cgit v1.1