From 02266e29f9250d74c5ec720aff23add3410ae920 Mon Sep 17 00:00:00 2001 From: Bob Wilson Date: Fri, 9 Jul 2010 16:37:18 +0000 Subject: --- Reverse-merging r107947 into '.': U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 195 ++++++++++---------------- 1 file changed, 76 insertions(+), 119 deletions(-) (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp') diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 924d939..5eb1a00 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -313,26 +313,6 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { // Determine if there is a call to setjmp in the machine function. MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); - // Replace forward-declared registers with the registers containing - // the desired value. - MachineRegisterInfo &MRI = MF->getRegInfo(); - for (DenseMap::iterator - I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); - I != E; ++I) { - unsigned From = I->first; - unsigned To = I->second; - // If To is also scheduled to be replaced, find what its ultimate - // replacement is. - for (;;) { - DenseMap::iterator J = - FuncInfo->RegFixups.find(To); - if (J == E) break; - To = J->second; - } - // Replace it. - MRI.replaceRegWith(From, To); - } - // Release function-specific state. SDB and CurDAG are already cleared // at this point. FuncInfo->clear(); @@ -340,8 +320,9 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { return true; } -void -SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, +MachineBasicBlock * +SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB, + BasicBlock::const_iterator Begin, BasicBlock::const_iterator End, bool &HadTailCall) { // Lower all of the non-terminator instructions. If a call is emitted @@ -356,7 +337,7 @@ SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, SDB->clear(); // Final step, emit the lowered DAG as machine code. - CodeGenAndEmitDAG(); + return CodeGenAndEmitDAG(BB); } namespace { @@ -445,7 +426,7 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() { } while (!Worklist.empty()); } -void SelectionDAGISel::CodeGenAndEmitDAG() { +MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) { std::string GroupName; if (TimePassesIsEnabled) GroupName = "Instruction Selection and Scheduling"; @@ -454,7 +435,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs) BlockName = MF->getFunction()->getNameStr() + ":" + - FuncInfo->MBB->getBasicBlock()->getNameStr(); + BB->getBasicBlock()->getNameStr(); DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump()); @@ -561,7 +542,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { { NamedRegionTimer T("Instruction Scheduling", GroupName, TimePassesIsEnabled); - Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt); + Scheduler->Run(CurDAG, BB, BB->end()); } if (ViewSUnitDAGs) Scheduler->viewGraph(); @@ -570,9 +551,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // inserted into. { NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); - - FuncInfo->MBB = Scheduler->EmitSchedule(); - FuncInfo->InsertPt = Scheduler->InsertPos; + BB = Scheduler->EmitSchedule(); } // Free the scheduler state. @@ -584,6 +563,8 @@ void SelectionDAGISel::CodeGenAndEmitDAG() { // Free the SelectionDAG state, now that we're finished with it. CurDAG->clear(); + + return BB; } void SelectionDAGISel::DoInstructionSelection() { @@ -645,22 +626,21 @@ void SelectionDAGISel::DoInstructionSelection() { /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and /// do other setup for EH landing-pad blocks. -void SelectionDAGISel::PrepareEHLandingPad() { +void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) { // Add a label to mark the beginning of the landing pad. Deletion of the // landing pad can thus be detected via the MachineModuleInfo. - MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); + MCSymbol *Label = MF->getMMI().addLandingPad(BB); const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); - BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) - .addSym(Label); + BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label); // Mark exception register as live in. unsigned Reg = TLI.getExceptionAddressRegister(); - if (Reg) FuncInfo->MBB->addLiveIn(Reg); + if (Reg) BB->addLiveIn(Reg); // Mark exception selector register as live in. Reg = TLI.getExceptionSelectorRegister(); - if (Reg) FuncInfo->MBB->addLiveIn(Reg); + if (Reg) BB->addLiveIn(Reg); // FIXME: Hack around an exception handling flaw (PR1508): the personality // function and list of typeids logically belong to the invoke (or, if you @@ -673,7 +653,7 @@ void SelectionDAGISel::PrepareEHLandingPad() { // in exceptions not being caught because no typeids are associated with // the invoke. This may not be the only way things can go wrong, but it // is the only way we try to work around for the moment. - const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock(); + const BasicBlock *LLVMBB = BB->getBasicBlock(); const BranchInst *Br = dyn_cast(LLVMBB->getTerminator()); if (Br && Br->isUnconditional()) { // Critical edge? @@ -697,95 +677,80 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { // Iterate over all basic blocks in the function. for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { const BasicBlock *LLVMBB = &*I; - FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; - FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); + MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB]; BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); BasicBlock::const_iterator const End = LLVMBB->end(); - BasicBlock::const_iterator BI = End; + BasicBlock::const_iterator BI = Begin; - FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); - - // Setup an EH landing-pad block. - if (FuncInfo->MBB->isLandingPad()) - PrepareEHLandingPad(); - // Lower any arguments needed in this block if this is the entry block. if (LLVMBB == &Fn.getEntryBlock()) LowerArguments(LLVMBB); + // Setup an EH landing-pad block. + if (BB->isLandingPad()) + PrepareEHLandingPad(BB); + // Before doing SelectionDAG ISel, see if FastISel has been requested. if (FastIS) { - FastIS->startNewBlock(); - // Emit code for any incoming arguments. This must happen before // beginning FastISel on the entry block. if (LLVMBB == &Fn.getEntryBlock()) { CurDAG->setRoot(SDB->getControlRoot()); SDB->clear(); - CodeGenAndEmitDAG(); - - // If we inserted any instructions at the beginning, make a note of - // where they are, so we can be sure to emit subsequent instructions - // after them. - if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) - FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); - else - FastIS->setLastLocalValue(0); + BB = CodeGenAndEmitDAG(BB); } - + FastIS->startNewBlock(BB); // Do FastISel on as many instructions as possible. - for (; BI != Begin; --BI) { - const Instruction *Inst = llvm::prior(BI); - - // If we no longer require this instruction, skip it. - if (!Inst->mayWriteToMemory() && - !isa(Inst) && - !isa(Inst) && - !FuncInfo->isExportedInst(Inst)) + for (; BI != End; ++BI) { +#if 0 + // Defer instructions with no side effects; they'll be emitted + // on-demand later. + if (BI->isSafeToSpeculativelyExecute() && + !FuncInfo->isExportedInst(BI)) continue; - - // Bottom-up: reset the insert pos at the top, after any local-value - // instructions. - FastIS->recomputeInsertPt(); +#endif // Try to select the instruction with FastISel. - if (FastIS->SelectInstruction(Inst)) + if (FastIS->SelectInstruction(BI)) continue; // Then handle certain instructions as single-LLVM-Instruction blocks. - if (isa(Inst)) { + if (isa(BI)) { ++NumFastIselFailures; if (EnableFastISelVerbose || EnableFastISelAbort) { dbgs() << "FastISel missed call: "; - Inst->dump(); + BI->dump(); } - if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { - unsigned &R = FuncInfo->ValueMap[Inst]; + if (!BI->getType()->isVoidTy() && !BI->use_empty()) { + unsigned &R = FuncInfo->ValueMap[BI]; if (!R) - R = FuncInfo->CreateRegs(Inst->getType()); + R = FuncInfo->CreateRegs(BI->getType()); } bool HadTailCall = false; - SelectBasicBlock(Inst, BI, HadTailCall); + BB = SelectBasicBlock(BB, BI, llvm::next(BI), HadTailCall); // If the call was emitted as a tail call, we're done with the block. if (HadTailCall) { - --BI; + BI = End; break; } + // If the instruction was codegen'd with multiple blocks, + // inform the FastISel object where to resume inserting. + FastIS->setCurrentBlock(BB); continue; } // Otherwise, give up on FastISel for the rest of the block. // For now, be a little lenient about non-branch terminators. - if (!isa(Inst) || isa(Inst)) { + if (!isa(BI) || isa(BI)) { ++NumFastIselFailures; if (EnableFastISelVerbose || EnableFastISelAbort) { dbgs() << "FastISel miss: "; - Inst->dump(); + BI->dump(); } if (EnableFastISelAbort) // The "fast" selector couldn't handle something and bailed. @@ -794,17 +759,17 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { } break; } - - FastIS->recomputeInsertPt(); } // Run SelectionDAG instruction selection on the remainder of the block // not handled by FastISel. If FastISel is not run, this is the entire // block. - bool HadTailCall; - SelectBasicBlock(Begin, BI, HadTailCall); + if (BI != End) { + bool HadTailCall; + BB = SelectBasicBlock(BB, BI, End, HadTailCall); + } - FinishBasicBlock(); + FinishBasicBlock(BB); FuncInfo->PHINodesToUpdate.clear(); } @@ -812,7 +777,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { } void -SelectionDAGISel::FinishBasicBlock() { +SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) { DEBUG(dbgs() << "Total amount of phi nodes to update: " << FuncInfo->PHINodesToUpdate.size() << "\n"; @@ -830,11 +795,11 @@ SelectionDAGISel::FinishBasicBlock() { MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; assert(PHI->isPHI() && "This is not a machine PHI node that we are updating!"); - if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) + if (!BB->isSuccessor(PHI->getParent())) continue; PHI->addOperand( MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); - PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); + PHI->addOperand(MachineOperand::CreateMBB(BB)); } return; } @@ -843,35 +808,33 @@ SelectionDAGISel::FinishBasicBlock() { // Lower header first, if it wasn't already lowered if (!SDB->BitTestCases[i].Emitted) { // Set the current basic block to the mbb we wish to insert the code into - FuncInfo->MBB = SDB->BitTestCases[i].Parent; - FuncInfo->InsertPt = FuncInfo->MBB->end(); + BB = SDB->BitTestCases[i].Parent; // Emit the code - SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); + SDB->visitBitTestHeader(SDB->BitTestCases[i], BB); CurDAG->setRoot(SDB->getRoot()); SDB->clear(); - CodeGenAndEmitDAG(); + BB = CodeGenAndEmitDAG(BB); } for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { // Set the current basic block to the mbb we wish to insert the code into - FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; - FuncInfo->InsertPt = FuncInfo->MBB->end(); + BB = SDB->BitTestCases[i].Cases[j].ThisBB; // Emit the code if (j+1 != ej) SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB, SDB->BitTestCases[i].Reg, SDB->BitTestCases[i].Cases[j], - FuncInfo->MBB); + BB); else SDB->visitBitTestCase(SDB->BitTestCases[i].Default, SDB->BitTestCases[i].Reg, SDB->BitTestCases[i].Cases[j], - FuncInfo->MBB); + BB); CurDAG->setRoot(SDB->getRoot()); SDB->clear(); - CodeGenAndEmitDAG(); + BB = CodeGenAndEmitDAG(BB); } // Update PHI Nodes @@ -916,24 +879,22 @@ SelectionDAGISel::FinishBasicBlock() { // Lower header first, if it wasn't already lowered if (!SDB->JTCases[i].first.Emitted) { // Set the current basic block to the mbb we wish to insert the code into - FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; - FuncInfo->InsertPt = FuncInfo->MBB->end(); + BB = SDB->JTCases[i].first.HeaderBB; // Emit the code SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, - FuncInfo->MBB); + BB); CurDAG->setRoot(SDB->getRoot()); SDB->clear(); - CodeGenAndEmitDAG(); + BB = CodeGenAndEmitDAG(BB); } // Set the current basic block to the mbb we wish to insert the code into - FuncInfo->MBB = SDB->JTCases[i].second.MBB; - FuncInfo->InsertPt = FuncInfo->MBB->end(); + BB = SDB->JTCases[i].second.MBB; // Emit the code SDB->visitJumpTable(SDB->JTCases[i].second); CurDAG->setRoot(SDB->getRoot()); SDB->clear(); - CodeGenAndEmitDAG(); + BB = CodeGenAndEmitDAG(BB); // Update PHI Nodes for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); @@ -951,11 +912,11 @@ SelectionDAGISel::FinishBasicBlock() { (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); } // JT BB. Just iterate over successors here - if (FuncInfo->MBB->isSuccessor(PHIBB)) { + if (BB->isSuccessor(PHIBB)) { PHI->addOperand (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, false)); - PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); + PHI->addOperand(MachineOperand::CreateMBB(BB)); } } } @@ -967,10 +928,10 @@ SelectionDAGISel::FinishBasicBlock() { MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; assert(PHI->isPHI() && "This is not a machine PHI node that we are updating!"); - if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { + if (BB->isSuccessor(PHI->getParent())) { PHI->addOperand( MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); - PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); + PHI->addOperand(MachineOperand::CreateMBB(BB)); } } @@ -978,8 +939,7 @@ SelectionDAGISel::FinishBasicBlock() { // additional DAGs necessary. for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { // Set the current basic block to the mbb we wish to insert the code into - MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; - FuncInfo->InsertPt = FuncInfo->MBB->end(); + MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB; // Determine the unique successors. SmallVector Succs; @@ -989,24 +949,21 @@ SelectionDAGISel::FinishBasicBlock() { // Emit the code. Note that this could result in ThisBB being split, so // we need to check for updates. - SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); + SDB->visitSwitchCase(SDB->SwitchCases[i], BB); CurDAG->setRoot(SDB->getRoot()); SDB->clear(); - CodeGenAndEmitDAG(); - ThisBB = FuncInfo->MBB; + ThisBB = CodeGenAndEmitDAG(BB); // Handle any PHI nodes in successors of this chunk, as if we were coming // from the original BB before switch expansion. Note that PHI nodes can // occur multiple times in PHINodesToUpdate. We have to be very careful to // handle them the right number of times. for (unsigned i = 0, e = Succs.size(); i != e; ++i) { - FuncInfo->MBB = Succs[i]; - FuncInfo->InsertPt = FuncInfo->MBB->end(); - // FuncInfo->MBB may have been removed from the CFG if a branch was - // constant folded. - if (ThisBB->isSuccessor(FuncInfo->MBB)) { - for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); - Phi != FuncInfo->MBB->end() && Phi->isPHI(); + BB = Succs[i]; + // BB may have been removed from the CFG if a branch was constant folded. + if (ThisBB->isSuccessor(BB)) { + for (MachineBasicBlock::iterator Phi = BB->begin(); + Phi != BB->end() && Phi->isPHI(); ++Phi) { // This value for this PHI node is recorded in PHINodesToUpdate. for (unsigned pn = 0; ; ++pn) { -- cgit v1.1