From 1436bb657d22b01fd9a526ee7f9b2cb880c064a7 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Fri, 30 Mar 2007 23:14:50 +0000 Subject: add one addressing mode description hook to rule them all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35520 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/TargetLowering.cpp | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp') diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 97c0939..5cd099c 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1940,6 +1940,40 @@ getRegForInlineAsmConstraint(const std::string &Constraint, // Loop Strength Reduction hooks //===----------------------------------------------------------------------===// +/// isLegalAddressingMode - Return true if the addressing mode represented +/// by AM is legal for this target, for a load/store of the specified type. +bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, + const Type *Ty) const { + // The default implementation of this implements a conservative RISCy, r+r and + // r+i addr mode. + + // Allows a sign-extended 16-bit immediate field. + if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) + return false; + + // No global is ever allowed as a base. + if (AM.BaseGV) + return false; + + // Only support r+r, + switch (AM.Scale) { + case 0: // "r+i" or just "i", depending on HasBaseReg. + break; + case 1: + if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. + return false; + // Otherwise we have r+r or r+i. + break; + case 2: + if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. + return false; + // Allow 2*r as r+r. + break; + } + + return true; +} + /// isLegalAddressImmediate - Return true if the integer value can be used as /// the offset of the target addressing mode for load / store of the given /// type. -- cgit v1.1