From 0b33cd55d1cfaa98fe4571d48caae4946a5e3a54 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 16 Apr 2009 20:57:10 +0000 Subject: Handle SUBREG_TO_REG instructions with the same heuristics as INSERT_SUBREG instructions in the list-burr scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69308 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'lib/CodeGen') diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 30dc476..d7a9636 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1019,9 +1019,10 @@ namespace { // avoid spilling. return 0; if (Opc == TargetInstrInfo::EXTRACT_SUBREG || + Opc == TargetInstrInfo::SUBREG_TO_REG || Opc == TargetInstrInfo::INSERT_SUBREG) - // EXTRACT_SUBREG / INSERT_SUBREG should be close to its use to - // facilitate coalescing. + // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be + // close to their uses to facilitate coalescing. return 0; if (SU->NumSuccs == 0 && SU->NumPreds != 0) // If SU does not have a register use, i.e. it doesn't produce a value @@ -1396,11 +1397,12 @@ void RegReductionPriorityQueue::AddPseudoTwoAddrDeps() { if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) continue; } - // Don't constrain extract_subreg / insert_subreg; these may be - // coalesced away. We want them close to their uses. + // Don't constrain EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG; + // these may be coalesced away. We want them close to their uses. unsigned SuccOpc = SuccSU->getNode()->getMachineOpcode(); if (SuccOpc == TargetInstrInfo::EXTRACT_SUBREG || - SuccOpc == TargetInstrInfo::INSERT_SUBREG) + SuccOpc == TargetInstrInfo::INSERT_SUBREG || + SuccOpc == TargetInstrInfo::SUBREG_TO_REG) continue; if ((!canClobber(SuccSU, DUSU) || (hasCopyToRegUse(SU) && !hasCopyToRegUse(SuccSU)) || -- cgit v1.1