From 42120a2c5546f0eca9fdedf860b6a222e279971a Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Thu, 14 Jun 2012 17:48:49 +0000 Subject: misched: disable SSA check pending PR13112. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158461 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/ScheduleDAGInstrs.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'lib/CodeGen') diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index 24b9cd0..110f478 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -413,8 +413,10 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { // SSA defs do not have output/anti dependencies. // The current operand is a def, so we have at least one. - if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) - return; + // + // FIXME: This optimization is disabled pending PR13112. + //if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end()) + // return; // Add output dependence to the next nearest def of this vreg. // -- cgit v1.1