From 3b148e5be8ac0683e53793cfa3761b4d84e3eda2 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 3 Apr 2013 00:33:32 +0000 Subject: This patch addresses PR15351 by explicitly checking for AVX support when getting the host processor information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178598 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index b9bbcb9..372b7fc 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -112,6 +112,18 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, #endif } +static bool OSHasAVXSupport() { +#if defined(__GNUC__) + int rEAX, rEDX; + __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); +#elif defined(_MSC_VER) + unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); +#else + int rEAX = 0; // Ensures we return false +#endif + return (rEAX & 6) == 6; +} + static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { Family = (EAX >> 8) & 0xf; // Bits 8 - 11 @@ -134,6 +146,10 @@ std::string sys::getHostCPUName() { DetectX86FamilyModel(EAX, Family, Model); bool HasSSE3 = (ECX & 0x1); + // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV + // indicates that the AVX registers will be saved and restored on context + // switch, when we have full AVX support. + bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport(); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); bool Em64T = (EDX >> 29) & 0x1; @@ -243,11 +259,15 @@ std::string sys::getHostCPUName() { case 42: // Intel Core i7 processor. All processors are manufactured // using the 32 nm process. case 45: - return "corei7-avx"; + // Not all Sandy Bridge processors support AVX (such as the Pentium + // versions instead of the i7 versions). + return HasAVX ? "corei7-avx" : "corei7"; // Ivy Bridge: case 58: - return "core-avx-i"; + // Not all Ivy Bridge processors support AVX (such as the Pentium + // versions instead of the i7 versions). + return HasAVX ? "core-avx-i" : "corei7"; case 28: // Most 45 nm Intel Atom processors case 38: // 45 nm Atom Lincroft -- cgit v1.1 From 95a16c4dbb26ecf4e7477eb4bb00a24b34402731 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 3 Apr 2013 01:39:37 +0000 Subject: Attempting to fix the build on older GCC versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178604 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index 372b7fc..c353cc6 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -113,7 +113,8 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, } static bool OSHasAVXSupport() { -#if defined(__GNUC__) +#if defined( __GNUC__ ) && \ + (__GNUC__ > 4 || __GNUC__ == 4 && __GNUC_MINOR__ >= 4) int rEAX, rEDX; __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); #elif defined(_MSC_VER) -- cgit v1.1 From 729c19482f434d8f3889d2a2c611a6e7813444f0 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 3 Apr 2013 03:11:39 +0000 Subject: Rolling back the AVX support patch due to breaking a gcc 4.6 build bot that doesn't understand the xgetbv instruction for some reason. Will revisit when time permits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178614 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index c353cc6..b9bbcb9 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -112,19 +112,6 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, #endif } -static bool OSHasAVXSupport() { -#if defined( __GNUC__ ) && \ - (__GNUC__ > 4 || __GNUC__ == 4 && __GNUC_MINOR__ >= 4) - int rEAX, rEDX; - __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); -#elif defined(_MSC_VER) - unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); -#else - int rEAX = 0; // Ensures we return false -#endif - return (rEAX & 6) == 6; -} - static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { Family = (EAX >> 8) & 0xf; // Bits 8 - 11 @@ -147,10 +134,6 @@ std::string sys::getHostCPUName() { DetectX86FamilyModel(EAX, Family, Model); bool HasSSE3 = (ECX & 0x1); - // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV - // indicates that the AVX registers will be saved and restored on context - // switch, when we have full AVX support. - bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport(); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); bool Em64T = (EDX >> 29) & 0x1; @@ -260,15 +243,11 @@ std::string sys::getHostCPUName() { case 42: // Intel Core i7 processor. All processors are manufactured // using the 32 nm process. case 45: - // Not all Sandy Bridge processors support AVX (such as the Pentium - // versions instead of the i7 versions). - return HasAVX ? "corei7-avx" : "corei7"; + return "corei7-avx"; // Ivy Bridge: case 58: - // Not all Ivy Bridge processors support AVX (such as the Pentium - // versions instead of the i7 versions). - return HasAVX ? "core-avx-i" : "corei7"; + return "core-avx-i"; case 28: // Most 45 nm Intel Atom processors case 38: // 45 nm Atom Lincroft -- cgit v1.1 From e1ecc5b0dbb85157ba70c4366deca3418fa0890a Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 3 Apr 2013 12:25:06 +0000 Subject: Second pass at addressing PR15351 by explicitly checking for AVX support when getting the host processor information. It emits a .byte sequence on GNUC compilers to work around lack of xgetbv support with older assemblers, and resolves a comment typo found in the previous patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178636 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index b9bbcb9..f91fb37 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -112,6 +112,21 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, #endif } +static bool OSHasAVXSupport() { +#if defined( __GNUC__ ) + // Check xgetbv; this uses a .byte sequence instead of the instruction + // directly because older assemblers do not include support for xgetbv and + // there is no easy way to conditionally compile based on the assembler used. + int rEAX, rEDX; + __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); +#elif defined(_MSC_VER) + unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); +#else + int rEAX = 0; // Ensures we return false +#endif + return (rEAX & 6) == 6; +} + static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) { Family = (EAX >> 8) & 0xf; // Bits 8 - 11 @@ -134,6 +149,10 @@ std::string sys::getHostCPUName() { DetectX86FamilyModel(EAX, Family, Model); bool HasSSE3 = (ECX & 0x1); + // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV + // indicates that the AVX registers will be saved and restored on context + // switch, then we have full AVX support. + bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport(); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); bool Em64T = (EDX >> 29) & 0x1; @@ -243,11 +262,15 @@ std::string sys::getHostCPUName() { case 42: // Intel Core i7 processor. All processors are manufactured // using the 32 nm process. case 45: - return "corei7-avx"; + // Not all Sandy Bridge processors support AVX (such as the Pentium + // versions instead of the i7 versions). + return HasAVX ? "corei7-avx" : "corei7"; // Ivy Bridge: case 58: - return "core-avx-i"; + // Not all Ivy Bridge processors support AVX (such as the Pentium + // versions instead of the i7 versions). + return HasAVX ? "core-avx-i" : "corei7"; case 28: // Most 45 nm Intel Atom processors case 38: // 45 nm Atom Lincroft -- cgit v1.1 From 1ac8f9073ce0fd0e247b477a427b35fa383cb3bd Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 3 Apr 2013 16:28:24 +0000 Subject: Testing for Visual Studio 2010 SP1 or greater before calling the _xgetbv intrinsic. This also fixes a minor code formatting issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178666 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index f91fb37..fef66e6 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -113,13 +113,13 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, } static bool OSHasAVXSupport() { -#if defined( __GNUC__ ) +#if defined(__GNUC__) // Check xgetbv; this uses a .byte sequence instead of the instruction // directly because older assemblers do not include support for xgetbv and // there is no easy way to conditionally compile based on the assembler used. int rEAX, rEDX; __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); -#elif defined(_MSC_VER) +#elif defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 160040219 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); #else int rEAX = 0; // Ensures we return false -- cgit v1.1 From b31b099a3722ad5b5d94ffe862ee92df51565b51 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Wed, 3 Apr 2013 18:00:22 +0000 Subject: Ensuring that both bits are set, and not just a combination of one or the other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178674 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index fef66e6..73d98d1 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -152,7 +152,8 @@ std::string sys::getHostCPUName() { // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV // indicates that the AVX registers will be saved and restored on context // switch, then we have full AVX support. - bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport(); + const unsigned AVXBits = (1 << 27) | (1 << 28); + bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport(); GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); bool Em64T = (EDX >> 29) & 0x1; -- cgit v1.1 From 80a1caa5cbe1980b861e944533e6d27f6d7e43a6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 22 Apr 2013 05:38:01 +0000 Subject: Convert windows line endings to linux/unix line endings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179995 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index 73d98d1..445b344 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -112,19 +112,19 @@ static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, #endif } -static bool OSHasAVXSupport() { -#if defined(__GNUC__) - // Check xgetbv; this uses a .byte sequence instead of the instruction - // directly because older assemblers do not include support for xgetbv and - // there is no easy way to conditionally compile based on the assembler used. - int rEAX, rEDX; - __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); -#elif defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 160040219 - unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); -#else - int rEAX = 0; // Ensures we return false -#endif - return (rEAX & 6) == 6; +static bool OSHasAVXSupport() { +#if defined(__GNUC__) + // Check xgetbv; this uses a .byte sequence instead of the instruction + // directly because older assemblers do not include support for xgetbv and + // there is no easy way to conditionally compile based on the assembler used. + int rEAX, rEDX; + __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); +#elif defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 160040219 + unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); +#else + int rEAX = 0; // Ensures we return false +#endif + return (rEAX & 6) == 6; } static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, -- cgit v1.1 From 3579a29dba8fcc7285a3a5bec4512b4ca0a91ab3 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Tue, 23 Apr 2013 17:38:44 +0000 Subject: Testing for _XCR_XFEATURE_ENABLED_MASK instead of a specific MSVC version because some MSVC 2010 SP1 installations do not have the _xgetbv intrinsic. Patch thanks to Serge Pavlov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180125 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Support/Host.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Support/Host.cpp') diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index 445b344..27c99c8 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -119,7 +119,7 @@ static bool OSHasAVXSupport() { // there is no easy way to conditionally compile based on the assembler used. int rEAX, rEDX; __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); -#elif defined(_MSC_FULL_VER) && _MSC_FULL_VER >= 160040219 +#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); #else int rEAX = 0; // Ensures we return false -- cgit v1.1