From d622bef31d11a5a6429fe7fad557c9b111e96f69 Mon Sep 17 00:00:00 2001
From: Hao Liu <Hao.Liu@arm.com>
Date: Thu, 10 Oct 2013 15:01:24 +0000
Subject: Implement AArch64 vector load/store multiple N-element structure
 class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load
 multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4:
 load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1
 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
 st2/st3/st4: store multiple N-element structure from sequential N registers
 (N = 2,3,4).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/AArch64/AArch64InstrFormats.td | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'lib/Target/AArch64/AArch64InstrFormats.td')

diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index 5781578..ab4d083 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1194,5 +1194,23 @@ class NeonI_Scalar2SameMisc<bit u, bits<2> size, bits<5> opcode, dag outs, dag i
   // Inherit Rd in 4-0
 }
 
+// Format AdvSIMD vector load/store multiple N-element structure
+class NeonI_LdStMult<bit q, bit l, bits<4> opcode, bits<2> size,
+                    dag outs, dag ins, string asmstr,
+                    list<dag> patterns, InstrItinClass itin>
+  : A64InstRtn<outs, ins, asmstr, patterns, itin>
+{
+  let Inst{31} = 0b0;
+  let Inst{30} = q;
+  let Inst{29-23} = 0b0011000;
+  let Inst{22} = l;
+  let Inst{21-16} = 0b000000;
+  let Inst{15-12} = opcode;
+  let Inst{11-10} = size;
+  
+  // Inherit Rn in 9-5
+  // Inherit Rt in 4-0
+}
+
 }
 
-- 
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