From 77b1c9cf57849b3f9a4e8bae47cd5954d20a7e11 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Mon, 11 Feb 2013 12:32:18 +0000 Subject: AArch64: Simplify logic in deciding whether bfi is valid Previous code had a confusing comment which was mostly an implementation detail. This condition corresponds to "lsb up to register width" and "width not ridiculous". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174877 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'lib/Target/AArch64/AsmParser') diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index bab7d84..1cdeafb 100644 --- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -1725,12 +1725,7 @@ validateInstruction(MCInst &Inst, int64_t ImmR = Inst.getOperand(ImmOps).getImm(); int64_t ImmS = Inst.getOperand(ImmOps+1).getImm(); - if (ImmR == 0) { - // Bitfield inserts are preferred disassembly if ImmS < ImmR. However, - // there is this one case where insert is valid syntax but the bfx - // disassembly should be used: e.g. "sbfiz w0, w0, #0, #1". - return false; - } else if (ImmS >= ImmR) { + if (ImmR != 0 && ImmS >= ImmR) { return Error(Operands[4]->getStartLoc(), "requested insert overflows register"); } -- cgit v1.1