From 837c28a84076e1cd63bbf29057b791ebe6b03de0 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Thu, 4 Oct 2012 21:33:24 +0000 Subject: ARM: locate user-defined text sections next to default text. Make sure functions located in user specified text sections (via the section attribute) are located together with the default text sections. Otherwise, for large object files, the relocations for call instructions are more likely to be out of range. This becomes even more likely in the presence of LTO. rdar://12402636 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165254 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index e9e2803..d14c10e 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -23,6 +23,8 @@ #include "InstPrinter/ARMInstPrinter.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMMCExpr.h" +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallString.h" #include "llvm/Constants.h" #include "llvm/DebugInfo.h" #include "llvm/Module.h" @@ -42,7 +44,6 @@ #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/ADT/SmallString.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -592,9 +593,24 @@ void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { const TargetLoweringObjectFileMachO &TLOFMacho = static_cast( getObjFileLowering()); - OutStreamer.SwitchSection(TLOFMacho.getTextSection()); - OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection()); - OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection()); + + // Collect the set of sections our functions will go into. + SetVector, + SmallPtrSet > TextSections; + // Default text section comes first. + TextSections.insert(TLOFMacho.getTextSection()); + // Now any user defined text sections from function attributes. + for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F) + if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage()) + TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM)); + // Now the coalescable sections. + TextSections.insert(TLOFMacho.getTextCoalSection()); + TextSections.insert(TLOFMacho.getConstTextCoalSection()); + + // Emit the sections in the .s file header to fix the order. + for (unsigned i = 0, e = TextSections.size(); i != e; ++i) + OutStreamer.SwitchSection(TextSections[i]); + if (RelocM == Reloc::DynamicNoPIC) { const MCSection *sect = OutContext.getMachOSection("__TEXT", "__symbol_stub4", -- cgit v1.1 From 3574eca1b02600bac4e625297f4ecf745f4c4f32 Mon Sep 17 00:00:00 2001 From: Micah Villmow Date: Mon, 8 Oct 2012 16:38:25 +0000 Subject: Move TargetData to DataLayout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index d14c10e..7d51657 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -42,7 +42,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/TargetData.h" +#include "llvm/DataLayout.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -303,7 +303,7 @@ void ARMAsmPrinter::EmitFunctionEntryLabel() { } void ARMAsmPrinter::EmitXXStructor(const Constant *CV) { - uint64_t Size = TM.getTargetData()->getTypeAllocSize(CV->getType()); + uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType()); assert(Size && "C++ constructor pointer had zero size!"); const GlobalValue *GV = dyn_cast(CV->stripPointerCasts()); @@ -909,7 +909,7 @@ MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) { void ARMAsmPrinter:: EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { - int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType()); + int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType()); ARMConstantPoolValue *ACPV = static_cast(MCPV); -- cgit v1.1 From 7747496736376c97d8bbf71302151287d1056abc Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 9 Oct 2012 04:23:49 +0000 Subject: Remove some dead code from ARMAsmPrinter. Add virtual and LLVM_OVERRIDE to the other methods. Mark some of the helper methods as private. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165479 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 7d51657..437d8e4 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -390,16 +390,6 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, //===--------------------------------------------------------------------===// MCSymbol *ARMAsmPrinter:: -GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2, - const MachineBasicBlock *MBB) const { - SmallString<60> Name; - raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() - << getFunctionNumber() << '_' << uid << '_' << uid2 - << "_set_" << MBB->getNumber(); - return OutContext.GetOrCreateSymbol(Name.str()); -} - -MCSymbol *ARMAsmPrinter:: GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const { SmallString<60> Name; raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI" @@ -1107,16 +1097,6 @@ static void populateADROperands(MCInst &Inst, unsigned Dest, Inst.addOperand(MCOperand::CreateReg(ccreg)); } -void ARMAsmPrinter::EmitPatchedInstruction(const MachineInstr *MI, - unsigned Opcode) { - MCInst TmpInst; - - // Emit the instruction as usual, just patch the opcode. - LowerARMMachineInstrToMCInst(MI, TmpInst, *this); - TmpInst.setOpcode(Opcode); - OutStreamer.EmitInstruction(TmpInst); -} - void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { assert(MI->getFlag(MachineInstr::FrameSetup) && "Only instruction which are involved into frame setup code are allowed"); -- cgit v1.1 From 19a1fcf8683a2a459a8aac93c1b4d1bf63b018fb Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Wed, 7 Nov 2012 18:01:03 +0000 Subject: Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167540 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 437d8e4..1d12b4f 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -749,13 +749,30 @@ void ARMAsmPrinter::emitAttributes() { AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed); } else if (CPUString == "generic") { - // FIXME: Why these defaults? - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); + // For a generic CPU, we assume a standard v7a architecture in Subtarget. + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, + ARMBuildAttrs::ApplicationProfile); AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, ARMBuildAttrs::Allowed); AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, - ARMBuildAttrs::Allowed); - } + ARMBuildAttrs::AllowThumb32); + } else if (Subtarget->hasV7Ops()) { + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); + AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, + ARMBuildAttrs::AllowThumb32); + } else if (Subtarget->hasV6T2Ops()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2); + else if (Subtarget->hasV6Ops()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6); + else if (Subtarget->hasV5TEOps()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE); + else if (Subtarget->hasV5TOps()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T); + else if (Subtarget->hasV4TOps()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); + else + llvm_unreachable("No target ARM architecture detected."); if (Subtarget->hasNEON() && emitFPU) { /* NEON is not exactly a VFP architecture, but GAS emit one of -- cgit v1.1 From 162d91c1e0bf5c14e2838dd623b3e054e7537de6 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Wed, 7 Nov 2012 18:57:14 +0000 Subject: Revert r167540 until regression tests are updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167545 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 1d12b4f..437d8e4 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -749,30 +749,13 @@ void ARMAsmPrinter::emitAttributes() { AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed); } else if (CPUString == "generic") { - // For a generic CPU, we assume a standard v7a architecture in Subtarget. - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, - ARMBuildAttrs::ApplicationProfile); + // FIXME: Why these defaults? + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, ARMBuildAttrs::Allowed); AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, - ARMBuildAttrs::AllowThumb32); - } else if (Subtarget->hasV7Ops()) { - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); - AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, - ARMBuildAttrs::AllowThumb32); - } else if (Subtarget->hasV6T2Ops()) - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2); - else if (Subtarget->hasV6Ops()) - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6); - else if (Subtarget->hasV5TEOps()) - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE); - else if (Subtarget->hasV5TOps()) - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T); - else if (Subtarget->hasV4TOps()) - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); - else - llvm_unreachable("No target ARM architecture detected."); + ARMBuildAttrs::Allowed); + } if (Subtarget->hasNEON() && emitFPU) { /* NEON is not exactly a VFP architecture, but GAS emit one of -- cgit v1.1 From 214fd3d2449738bbe0215dce24406dc29d9e49f7 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 8 Nov 2012 09:51:45 +0000 Subject: Recommit modified r167540. Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 437d8e4..8e55a44 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -749,13 +749,28 @@ void ARMAsmPrinter::emitAttributes() { AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed); } else if (CPUString == "generic") { - // FIXME: Why these defaults? - AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); + // For a generic CPU, we assume a standard v7a architecture in Subtarget. + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile, + ARMBuildAttrs::ApplicationProfile); AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, ARMBuildAttrs::Allowed); AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, - ARMBuildAttrs::Allowed); - } + ARMBuildAttrs::AllowThumb32); + } else if (Subtarget->hasV7Ops()) { + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7); + AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, + ARMBuildAttrs::AllowThumb32); + } else if (Subtarget->hasV6T2Ops()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2); + else if (Subtarget->hasV6Ops()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6); + else if (Subtarget->hasV5TEOps()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE); + else if (Subtarget->hasV5TOps()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T); + else if (Subtarget->hasV4TOps()) + AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T); if (Subtarget->hasNEON() && emitFPU) { /* NEON is not exactly a VFP architecture, but GAS emit one of -- cgit v1.1 From b341fac05a890272024dcc5c7e47d10b22d62b92 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 10 Nov 2012 02:09:05 +0000 Subject: Disable the Thumb no-return call optimization: mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 25 ------------------------- 1 file changed, 25 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 8e55a44..d439d1d 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1413,31 +1413,6 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } return; } - case ARM::t2BMOVPCB_CALL: { - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tMOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::t2B); - const GlobalValue *GV = MI->getOperand(0).getGlobal(); - MCSymbol *GVSym = Mang->getSymbol(GV); - const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); - TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr)); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - return; - } case ARM::MOVi16_ga_pcrel: case ARM::t2MOVi16_ga_pcrel: { MCInst TmpInst; -- cgit v1.1 From 79c07d2a36282b09b9c5d0aa65ebf4bff017621b Mon Sep 17 00:00:00 2001 From: Dmitri Gribenko Date: Thu, 15 Nov 2012 16:51:49 +0000 Subject: Use empty parens for empty function parameter list instead of '(void)'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168049 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index d439d1d..37cb646 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -398,7 +398,7 @@ GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const { } -MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const { +MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const { SmallString<60> Name; raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH" << getFunctionNumber(); -- cgit v1.1 From 391271f3bbcec02e0da26d7c246bfabff5cb4ddf Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Mon, 26 Nov 2012 13:34:22 +0000 Subject: Add MCInstBuilder, a utility class to simplify MCInst creation similar to MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 674 +++++++++++++++++---------------------- 1 file changed, 298 insertions(+), 376 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 37cb646..f32966d 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -37,6 +37,7 @@ #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstBuilder.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCObjectStreamer.h" #include "llvm/MC/MCStreamer.h" @@ -1051,12 +1052,11 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) { OutContext); // If this isn't a TBB or TBH, the entries are direct branch instructions. if (OffsetWidth == 4) { - MCInst BrInst; - BrInst.setOpcode(ARM::t2B); - BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); - BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - BrInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(BrInst); + MCInstBuilder(ARM::t2B) + .addExpr(MBBSymbolExpr) + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); continue; } // Otherwise it's an offset from the dispatch instruction. Construct an @@ -1100,18 +1100,6 @@ void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, printOperand(MI, NOps-2, OS); } -static void populateADROperands(MCInst &Inst, unsigned Dest, - const MCSymbol *Label, - unsigned pred, unsigned ccreg, - MCContext &Ctx) { - const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx); - Inst.addOperand(MCOperand::CreateReg(Dest)); - Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); - // Add predicate operands. - Inst.addOperand(MCOperand::CreateImm(pred)); - Inst.addOperand(MCOperand::CreateReg(ccreg)); -} - void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { assert(MI->getFlag(MachineInstr::FrameSetup) && "Only instruction which are involved into frame setup code are allowed"); @@ -1288,129 +1276,112 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::tLEApcrel: case ARM::t2LEApcrel: { // FIXME: Need to also handle globals and externals - MCInst TmpInst; - TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR - : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR - : ARM::ADR)); - populateADROperands(TmpInst, MI->getOperand(0).getReg(), - GetCPISymbol(MI->getOperand(1).getIndex()), - MI->getOperand(2).getImm(), MI->getOperand(3).getReg(), - OutContext); - OutStreamer.EmitInstruction(TmpInst); + MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex()); + MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR + : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR + : ARM::ADR)) + .addReg(MI->getOperand(0).getReg()) + .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext)) + // Add predicate operands. + .addImm(MI->getOperand(2).getImm()) + .addReg(MI->getOperand(3).getReg()) + .emit(OutStreamer); return; } case ARM::LEApcrelJT: case ARM::tLEApcrelJT: case ARM::t2LEApcrelJT: { - MCInst TmpInst; - TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR - : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR - : ARM::ADR)); - populateADROperands(TmpInst, MI->getOperand(0).getReg(), - GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(), - MI->getOperand(2).getImm()), - MI->getOperand(3).getImm(), MI->getOperand(4).getReg(), - OutContext); - OutStreamer.EmitInstruction(TmpInst); + MCSymbol *JTIPICSymbol = + GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(), + MI->getOperand(2).getImm()); + MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR + : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR + : ARM::ADR)) + .addReg(MI->getOperand(0).getReg()) + .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext)) + // Add predicate operands. + .addImm(MI->getOperand(3).getImm()) + .addReg(MI->getOperand(4).getReg()) + .emit(OutStreamer); return; } // Darwin call instructions are just normal call instructions with different // clobber semantics (they clobber R9). case ARM::BX_CALL: { - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); + MCInstBuilder(ARM::MOVr) + .addReg(ARM::LR) + .addReg(ARM::PC) // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // Add 's' bit operand (always reg0 for this) - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::BX); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - OutStreamer.EmitInstruction(TmpInst); - } + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::BX) + .addReg(MI->getOperand(0).getReg()) + .emit(OutStreamer); return; } case ARM::tBX_CALL: { - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tMOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); + MCInstBuilder(ARM::tMOVr) + .addReg(ARM::LR) + .addReg(ARM::PC) // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tBX); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tBX) + .addReg(MI->getOperand(0).getReg()) // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); return; } case ARM::BMOVPCRX_CALL: { - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); + MCInstBuilder(ARM::MOVr) + .addReg(ARM::LR) + .addReg(ARM::PC) // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // Add 's' bit operand (always reg0 for this) - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::MOVr) + .addReg(ARM::PC) + .addImm(MI->getOperand(0).getReg()) // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // Add 's' bit operand (always reg0 for this) - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } + .addReg(0) + .emit(OutStreamer); return; } case ARM::BMOVPCB_CALL: { - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); + MCInstBuilder(ARM::MOVr) + .addReg(ARM::LR) + .addReg(ARM::PC) // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // Add 's' bit operand (always reg0 for this) - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::Bcc); - const GlobalValue *GV = MI->getOperand(0).getGlobal(); - MCSymbol *GVSym = Mang->getSymbol(GV); - const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); - TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr)); + .addReg(0) + .emit(OutStreamer); + + const GlobalValue *GV = MI->getOperand(0).getGlobal(); + MCSymbol *GVSym = Mang->getSymbol(GV); + const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); + MCInstBuilder(ARM::Bcc) + .addExpr(GVSymExpr) // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); return; } case ARM::MOVi16_ga_pcrel: @@ -1498,15 +1469,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext)); // Form and emit the add. - MCInst AddInst; - AddInst.setOpcode(ARM::tADDhirr); - AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); - // Add predicate operands. - AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - AddInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(AddInst); + MCInstBuilder(ARM::tADDhirr) + .addReg(MI->getOperand(0).getReg()) + .addReg(MI->getOperand(0).getReg()) + .addReg(ARM::PC) + // Add predicate operands. + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); return; } case ARM::PICADD: { @@ -1521,17 +1491,16 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext)); // Form and emit the add. - MCInst AddInst; - AddInst.setOpcode(ARM::ADDrr); - AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - AddInst.addOperand(MCOperand::CreateReg(ARM::PC)); - AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); - // Add predicate operands. - AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); - AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); - // Add 's' bit operand (always reg0 for this) - AddInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(AddInst); + MCInstBuilder(ARM::ADDrr) + .addReg(MI->getOperand(0).getReg()) + .addReg(ARM::PC) + .addReg(MI->getOperand(1).getReg()) + // Add predicate operands. + .addImm(MI->getOperand(3).getImm()) + .addReg(MI->getOperand(4).getReg()) + // Add 's' bit operand (always reg0 for this) + .addReg(0) + .emit(OutStreamer); return; } case ARM::PICSTR: @@ -1567,16 +1536,15 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; } - MCInst LdStInst; - LdStInst.setOpcode(Opcode); - LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - LdStInst.addOperand(MCOperand::CreateReg(ARM::PC)); - LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); - LdStInst.addOperand(MCOperand::CreateImm(0)); - // Add predicate operands. - LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm())); - LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg())); - OutStreamer.EmitInstruction(LdStInst); + MCInstBuilder(Opcode) + .addReg(MI->getOperand(0).getReg()) + .addReg(ARM::PC) + .addReg(MI->getOperand(1).getReg()) + .addImm(0) + // Add predicate operands. + .addImm(MI->getOperand(3).getImm()) + .addReg(MI->getOperand(4).getReg()) + .emit(OutStreamer); return; } @@ -1606,29 +1574,28 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2BR_JT: { // Lower and emit the instruction itself, then the jump table following it. - MCInst TmpInst; - TmpInst.setOpcode(ARM::tMOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); + MCInstBuilder(ARM::tMOVr) + .addReg(ARM::PC) + .addReg(MI->getOperand(0).getReg()) + // Add predicate operands. + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + // Output the data for the jump table itself EmitJump2Table(MI); return; } case ARM::t2TBB_JT: { // Lower and emit the instruction itself, then the jump table following it. - MCInst TmpInst; + MCInstBuilder(ARM::t2TBB) + .addReg(ARM::PC) + .addReg(MI->getOperand(0).getReg()) + // Add predicate operands. + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); - TmpInst.setOpcode(ARM::t2TBB); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); // Output the data for the jump table itself EmitJump2Table(MI); // Make sure the next instruction is 2-byte aligned. @@ -1637,15 +1604,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2TBH_JT: { // Lower and emit the instruction itself, then the jump table following it. - MCInst TmpInst; + MCInstBuilder(ARM::t2TBH) + .addReg(ARM::PC) + .addReg(MI->getOperand(0).getReg()) + // Add predicate operands. + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); - TmpInst.setOpcode(ARM::t2TBH); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); // Output the data for the jump table itself EmitJump2Table(MI); return; @@ -1705,17 +1671,16 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::BR_JTadd: { // Lower and emit the instruction itself, then the jump table following it. // add pc, target, idx - MCInst TmpInst; - TmpInst.setOpcode(ARM::ADDrr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); - TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg())); - // Add predicate operands. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - // Add 's' bit operand (always reg0 for this) - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); + MCInstBuilder(ARM::ADDrr) + .addReg(ARM::PC) + .addReg(MI->getOperand(0).getReg()) + .addReg(MI->getOperand(1).getReg()) + // Add predicate operands. + .addImm(ARMCC::AL) + .addReg(0) + // Add 's' bit operand (always reg0 for this) + .addReg(0) + .emit(OutStreamer); // Output the data for the jump table itself EmitJumpTable(MI); @@ -1759,75 +1724,63 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ValReg = MI->getOperand(1).getReg(); MCSymbol *Label = GetARMSJLJEHLabel(); - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tMOVr); - TmpInst.addOperand(MCOperand::CreateReg(ValReg)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); + OutStreamer.AddComment("eh_setjmp begin"); + MCInstBuilder(ARM::tMOVr) + .addReg(ValReg) + .addReg(ARM::PC) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.AddComment("eh_setjmp begin"); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tADDi3); - TmpInst.addOperand(MCOperand::CreateReg(ValReg)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tADDi3) + .addReg(ValReg) // 's' bit operand - TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR)); - TmpInst.addOperand(MCOperand::CreateReg(ValReg)); - TmpInst.addOperand(MCOperand::CreateImm(7)); + .addReg(ARM::CPSR) + .addReg(ValReg) + .addImm(7) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tSTRi); - TmpInst.addOperand(MCOperand::CreateReg(ValReg)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tSTRi) + .addReg(ValReg) + .addReg(SrcReg) // The offset immediate is #4. The operand value is scaled by 4 for the // tSTR instruction. - TmpInst.addOperand(MCOperand::CreateImm(1)); + .addImm(1) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tMOVi8); - TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR)); - TmpInst.addOperand(MCOperand::CreateImm(0)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tMOVi8) + .addReg(ARM::R0) + .addReg(ARM::CPSR) + .addImm(0) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext); - MCInst TmpInst; - TmpInst.setOpcode(ARM::tB); - TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr)); - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tMOVi8); - TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR)); - TmpInst.addOperand(MCOperand::CreateImm(1)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext); + MCInstBuilder(ARM::tB) + .addExpr(SymbolExpr) + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + OutStreamer.AddComment("eh_setjmp end"); + MCInstBuilder(ARM::tMOVi8) + .addReg(ARM::R0) + .addReg(ARM::CPSR) + .addImm(1) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.AddComment("eh_setjmp end"); - OutStreamer.EmitInstruction(TmpInst); - } + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + OutStreamer.EmitLabel(Label); return; } @@ -1843,69 +1796,58 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ValReg = MI->getOperand(1).getReg(); - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::ADDri); - TmpInst.addOperand(MCOperand::CreateReg(ValReg)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateImm(8)); + OutStreamer.AddComment("eh_setjmp begin"); + MCInstBuilder(ARM::ADDri) + .addReg(ValReg) + .addReg(ARM::PC) + .addImm(8) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // 's' bit operand (always reg0 for this). - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.AddComment("eh_setjmp begin"); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::STRi12); - TmpInst.addOperand(MCOperand::CreateReg(ValReg)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateImm(4)); + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::STRi12) + .addReg(ValReg) + .addReg(SrcReg) + .addImm(4) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVi); - TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); - TmpInst.addOperand(MCOperand::CreateImm(0)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::MOVi) + .addReg(ARM::R0) + .addImm(0) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // 's' bit operand (always reg0 for this). - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::ADDri); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); - TmpInst.addOperand(MCOperand::CreateImm(0)); + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::ADDri) + .addReg(ARM::PC) + .addReg(ARM::PC) + .addImm(0) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // 's' bit operand (always reg0 for this). - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVi); - TmpInst.addOperand(MCOperand::CreateReg(ARM::R0)); - TmpInst.addOperand(MCOperand::CreateImm(1)); + .addReg(0) + .emit(OutStreamer); + + OutStreamer.AddComment("eh_setjmp end"); + MCInstBuilder(ARM::MOVi) + .addReg(ARM::R0) + .addImm(1) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); + .addImm(ARMCC::AL) + .addReg(0) // 's' bit operand (always reg0 for this). - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.AddComment("eh_setjmp end"); - OutStreamer.EmitInstruction(TmpInst); - } + .addReg(0) + .emit(OutStreamer); return; } case ARM::Int_eh_sjlj_longjmp: { @@ -1915,48 +1857,39 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // bx $scratch unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg(); - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::LDRi12); - TmpInst.addOperand(MCOperand::CreateReg(ARM::SP)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateImm(8)); + MCInstBuilder(ARM::LDRi12) + .addReg(ARM::SP) + .addReg(SrcReg) + .addImm(8) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::LDRi12); - TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateImm(4)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::LDRi12) + .addReg(ScratchReg) + .addReg(SrcReg) + .addImm(4) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::LDRi12); - TmpInst.addOperand(MCOperand::CreateReg(ARM::R7)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateImm(0)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::LDRi12) + .addReg(ARM::R7) + .addReg(SrcReg) + .addImm(0) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::BX); - TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::BX) + .addReg(ScratchReg) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); return; } case ARM::tInt_eh_sjlj_longjmp: { @@ -1967,60 +1900,49 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // bx $scratch unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg(); - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tLDRi); - TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); + MCInstBuilder(ARM::tLDRi) + .addReg(ScratchReg) + .addReg(SrcReg) // The offset immediate is #8. The operand value is scaled by 4 for the // tLDR instruction. - TmpInst.addOperand(MCOperand::CreateImm(2)); + .addImm(2) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tMOVr); - TmpInst.addOperand(MCOperand::CreateReg(ARM::SP)); - TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tMOVr) + .addReg(ARM::SP) + .addReg(ScratchReg) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tLDRi); - TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateImm(1)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tLDRi) + .addReg(ScratchReg) + .addReg(SrcReg) + .addImm(1) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tLDRi); - TmpInst.addOperand(MCOperand::CreateReg(ARM::R7)); - TmpInst.addOperand(MCOperand::CreateReg(SrcReg)); - TmpInst.addOperand(MCOperand::CreateImm(0)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tLDRi) + .addReg(ARM::R7) + .addReg(SrcReg) + .addImm(0) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } - { - MCInst TmpInst; - TmpInst.setOpcode(ARM::tBX); - TmpInst.addOperand(MCOperand::CreateReg(ScratchReg)); + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); + + MCInstBuilder(ARM::tBX) + .addReg(ScratchReg) // Predicate. - TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); - TmpInst.addOperand(MCOperand::CreateReg(0)); - OutStreamer.EmitInstruction(TmpInst); - } + .addImm(ARMCC::AL) + .addReg(0) + .emit(OutStreamer); return; } } -- cgit v1.1 From ed9e442cf098663ce213cb16778b44be466b441f Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Mon, 26 Nov 2012 18:05:52 +0000 Subject: Decouple MCInstBuilder from the streamer per Eli's request. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 192 ++++++++++++++++----------------------- 1 file changed, 78 insertions(+), 114 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index f32966d..7d48bc1 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1052,11 +1052,10 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) { OutContext); // If this isn't a TBB or TBH, the entries are direct branch instructions. if (OffsetWidth == 4) { - MCInstBuilder(ARM::t2B) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B) .addExpr(MBBSymbolExpr) .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); continue; } // Otherwise it's an offset from the dispatch instruction. Construct an @@ -1277,15 +1276,15 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::t2LEApcrel: { // FIXME: Need to also handle globals and externals MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex()); - MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR + OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() == + ARM::t2LEApcrel ? ARM::t2ADR : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR : ARM::ADR)) .addReg(MI->getOperand(0).getReg()) .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext)) // Add predicate operands. .addImm(MI->getOperand(2).getImm()) - .addReg(MI->getOperand(3).getReg()) - .emit(OutStreamer); + .addReg(MI->getOperand(3).getReg())); return; } case ARM::LEApcrelJT: @@ -1294,94 +1293,86 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { MCSymbol *JTIPICSymbol = GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(), MI->getOperand(2).getImm()); - MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR + OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() == + ARM::t2LEApcrelJT ? ARM::t2ADR : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR : ARM::ADR)) .addReg(MI->getOperand(0).getReg()) .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext)) // Add predicate operands. .addImm(MI->getOperand(3).getImm()) - .addReg(MI->getOperand(4).getReg()) - .emit(OutStreamer); + .addReg(MI->getOperand(4).getReg())); return; } // Darwin call instructions are just normal call instructions with different // clobber semantics (they clobber R9). case ARM::BX_CALL: { - MCInstBuilder(ARM::MOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. .addImm(ARMCC::AL) .addReg(0) // Add 's' bit operand (always reg0 for this) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::BX) - .addReg(MI->getOperand(0).getReg()) - .emit(OutStreamer); + OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX) + .addReg(MI->getOperand(0).getReg())); return; } case ARM::tBX_CALL: { - MCInstBuilder(ARM::tMOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tBX) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } case ARM::BMOVPCRX_CALL: { - MCInstBuilder(ARM::MOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. .addImm(ARMCC::AL) .addReg(0) // Add 's' bit operand (always reg0 for this) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::MOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) .addReg(ARM::PC) .addImm(MI->getOperand(0).getReg()) // Add predicate operands. .addImm(ARMCC::AL) .addReg(0) // Add 's' bit operand (always reg0 for this) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } case ARM::BMOVPCB_CALL: { - MCInstBuilder(ARM::MOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr) .addReg(ARM::LR) .addReg(ARM::PC) // Add predicate operands. .addImm(ARMCC::AL) .addReg(0) // Add 's' bit operand (always reg0 for this) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); const GlobalValue *GV = MI->getOperand(0).getGlobal(); MCSymbol *GVSym = Mang->getSymbol(GV); const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext); - MCInstBuilder(ARM::Bcc) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc) .addExpr(GVSymExpr) // Add predicate operands. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } case ARM::MOVi16_ga_pcrel: @@ -1469,14 +1460,13 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext)); // Form and emit the add. - MCInstBuilder(ARM::tADDhirr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(0).getReg()) .addReg(ARM::PC) // Add predicate operands. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } case ARM::PICADD: { @@ -1491,7 +1481,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { OutContext)); // Form and emit the add. - MCInstBuilder(ARM::ADDrr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr) .addReg(MI->getOperand(0).getReg()) .addReg(ARM::PC) .addReg(MI->getOperand(1).getReg()) @@ -1499,8 +1489,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(MI->getOperand(3).getImm()) .addReg(MI->getOperand(4).getReg()) // Add 's' bit operand (always reg0 for this) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } case ARM::PICSTR: @@ -1536,15 +1525,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::PICLDRSB: Opcode = ARM::LDRSB; break; case ARM::PICLDRSH: Opcode = ARM::LDRSH; break; } - MCInstBuilder(Opcode) + OutStreamer.EmitInstruction(MCInstBuilder(Opcode) .addReg(MI->getOperand(0).getReg()) .addReg(ARM::PC) .addReg(MI->getOperand(1).getReg()) .addImm(0) // Add predicate operands. .addImm(MI->getOperand(3).getImm()) - .addReg(MI->getOperand(4).getReg()) - .emit(OutStreamer); + .addReg(MI->getOperand(4).getReg())); return; } @@ -1574,13 +1562,12 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2BR_JT: { // Lower and emit the instruction itself, then the jump table following it. - MCInstBuilder(ARM::tMOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); // Output the data for the jump table itself EmitJump2Table(MI); @@ -1588,13 +1575,12 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2TBB_JT: { // Lower and emit the instruction itself, then the jump table following it. - MCInstBuilder(ARM::t2TBB) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); // Output the data for the jump table itself EmitJump2Table(MI); @@ -1604,13 +1590,12 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { } case ARM::t2TBH_JT: { // Lower and emit the instruction itself, then the jump table following it. - MCInstBuilder(ARM::t2TBH) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) // Add predicate operands. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); // Output the data for the jump table itself EmitJump2Table(MI); @@ -1671,7 +1656,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM::BR_JTadd: { // Lower and emit the instruction itself, then the jump table following it. // add pc, target, idx - MCInstBuilder(ARM::ADDrr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr) .addReg(ARM::PC) .addReg(MI->getOperand(0).getReg()) .addReg(MI->getOperand(1).getReg()) @@ -1679,8 +1664,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0) // Add 's' bit operand (always reg0 for this) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); // Output the data for the jump table itself EmitJumpTable(MI); @@ -1725,15 +1709,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned ValReg = MI->getOperand(1).getReg(); MCSymbol *Label = GetARMSJLJEHLabel(); OutStreamer.AddComment("eh_setjmp begin"); - MCInstBuilder(ARM::tMOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) .addReg(ValReg) .addReg(ARM::PC) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tADDi3) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3) .addReg(ValReg) // 's' bit operand .addReg(ARM::CPSR) @@ -1741,10 +1724,9 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(7) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tSTRi) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi) .addReg(ValReg) .addReg(SrcReg) // The offset immediate is #4. The operand value is scaled by 4 for the @@ -1752,34 +1734,30 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(1) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tMOVi8) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8) .addReg(ARM::R0) .addReg(ARM::CPSR) .addImm(0) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext); - MCInstBuilder(ARM::tB) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB) .addExpr(SymbolExpr) .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); OutStreamer.AddComment("eh_setjmp end"); - MCInstBuilder(ARM::tMOVi8) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8) .addReg(ARM::R0) .addReg(ARM::CPSR) .addImm(1) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); OutStreamer.EmitLabel(Label); return; @@ -1797,7 +1775,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { unsigned ValReg = MI->getOperand(1).getReg(); OutStreamer.AddComment("eh_setjmp begin"); - MCInstBuilder(ARM::ADDri) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri) .addReg(ValReg) .addReg(ARM::PC) .addImm(8) @@ -1805,29 +1783,26 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0) // 's' bit operand (always reg0 for this). - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::STRi12) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12) .addReg(ValReg) .addReg(SrcReg) .addImm(4) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::MOVi) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi) .addReg(ARM::R0) .addImm(0) // Predicate. .addImm(ARMCC::AL) .addReg(0) // 's' bit operand (always reg0 for this). - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::ADDri) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri) .addReg(ARM::PC) .addReg(ARM::PC) .addImm(0) @@ -1835,19 +1810,17 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(ARMCC::AL) .addReg(0) // 's' bit operand (always reg0 for this). - .addReg(0) - .emit(OutStreamer); + .addReg(0)); OutStreamer.AddComment("eh_setjmp end"); - MCInstBuilder(ARM::MOVi) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi) .addReg(ARM::R0) .addImm(1) // Predicate. .addImm(ARMCC::AL) .addReg(0) // 's' bit operand (always reg0 for this). - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } case ARM::Int_eh_sjlj_longjmp: { @@ -1857,39 +1830,35 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // bx $scratch unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg(); - MCInstBuilder(ARM::LDRi12) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) .addReg(ARM::SP) .addReg(SrcReg) .addImm(8) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::LDRi12) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) .addReg(ScratchReg) .addReg(SrcReg) .addImm(4) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::LDRi12) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12) .addReg(ARM::R7) .addReg(SrcReg) .addImm(0) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::BX) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX) .addReg(ScratchReg) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } case ARM::tInt_eh_sjlj_longjmp: { @@ -1900,7 +1869,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { // bx $scratch unsigned SrcReg = MI->getOperand(0).getReg(); unsigned ScratchReg = MI->getOperand(1).getReg(); - MCInstBuilder(ARM::tLDRi) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) .addReg(ScratchReg) .addReg(SrcReg) // The offset immediate is #8. The operand value is scaled by 4 for the @@ -1908,41 +1877,36 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { .addImm(2) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tMOVr) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr) .addReg(ARM::SP) .addReg(ScratchReg) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tLDRi) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) .addReg(ScratchReg) .addReg(SrcReg) .addImm(1) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tLDRi) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi) .addReg(ARM::R7) .addReg(SrcReg) .addImm(0) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); - MCInstBuilder(ARM::tBX) + OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX) .addReg(ScratchReg) // Predicate. .addImm(ARMCC::AL) - .addReg(0) - .emit(OutStreamer); + .addReg(0)); return; } } -- cgit v1.1 From d04a8d4b33ff316ca4cf961e06c9e312eff8e64f Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Mon, 3 Dec 2012 16:50:05 +0000 Subject: Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 7d48bc1..2ecd464 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -25,31 +25,31 @@ #include "MCTargetDesc/ARMMCExpr.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallString.h" -#include "llvm/Constants.h" -#include "llvm/DebugInfo.h" -#include "llvm/Module.h" -#include "llvm/Type.h" #include "llvm/Assembly/Writer.h" -#include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" +#include "llvm/CodeGen/MachineModuleInfoImpls.h" +#include "llvm/Constants.h" +#include "llvm/DataLayout.h" +#include "llvm/DebugInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstBuilder.h" -#include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCObjectStreamer.h" +#include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/Target/Mangler.h" -#include "llvm/DataLayout.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/Module.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Target/Mangler.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Type.h" #include using namespace llvm; -- cgit v1.1 From 0b8c9a80f20772c3793201ab5b251d3520b9cea3 Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Wed, 2 Jan 2013 11:36:10 +0000 Subject: Move all of the header files which are involved in modelling the LLVM IR into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMAsmPrinter.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp') diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 2ecd464..fc6ac90 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -29,9 +29,11 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" -#include "llvm/Constants.h" -#include "llvm/DataLayout.h" #include "llvm/DebugInfo.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/Type.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" @@ -41,7 +43,6 @@ #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" -#include "llvm/Module.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -49,7 +50,6 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Type.h" #include using namespace llvm; -- cgit v1.1