From e921f323533ee751b3fa34bd00d10fa72096ffd3 Mon Sep 17 00:00:00 2001 From: Mihai Popa Date: Fri, 9 Aug 2013 10:38:32 +0000 Subject: Fix assembling of Thumb2 branch instructions. The long encoding for Thumb2 unconditional branches is broken. Additionally, there is no range checking for target operands; as such for instructions originating in assembly code, only short Thumb encodings are generated, regardless of the bitsize needed for the offset. Adding range checking is non trivial due to the representation of Thumb branch instructions. There is no true difference between conditional and unconditional branches in terms of operands and syntax - even unconditional branches have a predicate which is expected to match that of the IT block they are in. Yet, the encodings and the permitted size of the offset differ. Due to this, for any mnemonic there are really 4 encodings to choose for. The problem cannot be handled in the parser alone or by manipulating td files. Because the parser builds first a set of match candidates and then checks them one by one, whatever tablegen-only solution might be found will ultimately be dependent of the parser's evaluation order. What's worse is that due to the fact that all branches have the same syntax and the same kinds of operands, that order is governed by the lexicographical ordering of the names of operand classes... To circumvent all this, any necessary disambiguation is added to the instruction validation pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index e7218c6..d5b6563 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -491,7 +491,8 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in { T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { bits<11> target; let Inst{10-0} = target; - } + let AsmMatchConverter = "cvtThumbBranches"; + } // Far jump // Just a pseudo for a tBL instruction. Needed to let regalloc know about @@ -521,6 +522,7 @@ let isBranch = 1, isTerminator = 1 in bits<8> target; let Inst{11-8} = p; let Inst{7-0} = target; + let AsmMatchConverter = "cvtThumbBranches"; } -- cgit v1.1 From 428715d4e120e6ef6fc898665607a92f3dd02709 Mon Sep 17 00:00:00 2001 From: Mihai Popa Date: Thu, 15 Aug 2013 15:43:06 +0000 Subject: This fixes three issues related to Thumb literal loads: 1. The offset range for Thumb1 PC relative loads is [0..1020] and not [-1024..1020] 2. Thumb2 PC relative loads may define the PC, so the restriction placed on target register is removed 3. Removes unneeded alias between "ldr.n" and t1LDRpci. ".n" is actually stripped by both tablegen and the ASM parser, so this alias rule really does nothing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188466 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 3 --- 1 file changed, 3 deletions(-) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index d5b6563..7e383d2 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -662,9 +662,6 @@ def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, let Inst{7-0} = addr; } -def : tInstAlias<"ldr${p}.n $Rt, $addr", - (tLDRpci tGPR:$Rt, t_addrmode_pc:$addr, pred:$p), 0>; - // A8.6.194 & A8.6.192 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, t_addrmode_is4, AddrModeT1_4, -- cgit v1.1 From f7ab3a84b3e1b5a647ae9456a5edb99d86b35329 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Thu, 22 Aug 2013 09:57:11 +0000 Subject: ARM: use TableGen patterns to select CMOV operations. Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 7e383d2..291b98a 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -1204,9 +1204,9 @@ def tUXTH : // A8.6.264 // Expanded after instruction selection into a branch sequence. let usesCustomInserter = 1 in // Expanded after instruction selection. def tMOVCCr_pseudo : - PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), - NoItinerary, - [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; + PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), + NoItinerary, + [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; // tLEApcrel - Load a pc-relative address into a register without offending the // assembler. -- cgit v1.1 From b5523ce1bb50e86942ad5273e3a89872c4d26b73 Mon Sep 17 00:00:00 2001 From: Richard Barton Date: Thu, 5 Sep 2013 14:14:19 +0000 Subject: Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 291b98a..dd5f2cf 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -300,6 +300,13 @@ def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", let Inst{7-0} = val; } +def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", + []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { + let Inst{9-6} = 0b1010; + bits<6> val; + let Inst{5-0} = val; +} + def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", []>, T1Encoding<0b101101> { bits<1> end; -- cgit v1.1 From d1311ac171f9cb90cab4906a6c0e091b6b65b862 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Tue, 1 Oct 2013 12:39:11 +0000 Subject: [ARM] Introduce the 'sevl' instruction in ARMv8. This also removes the restriction on the immediate field of the 'hint' instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191744 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index dd5f2cf..2c54791 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -289,6 +289,11 @@ def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, T1SystemEncoding<0x40>, // A8.6.157 Requires<[IsThumb2]>; +def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>, + T1SystemEncoding<0x50>, + Requires<[IsThumb2, HasV8]>; + + // The imm operand $val can be used by a debugger to store more information // about the breakpoint. def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", -- cgit v1.1 From 6eef361b73b457896b310d411251aedd5e72476a Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Thu, 3 Oct 2013 09:31:51 +0000 Subject: [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly. Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 2c54791..458254e 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -313,7 +313,7 @@ def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", } def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", - []>, T1Encoding<0b101101> { + []>, T1Encoding<0b101101>, Deprecated { bits<1> end; // A8.6.156 let Inst{9-5} = 0b10010; -- cgit v1.1 From cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Mon, 7 Oct 2013 11:10:47 +0000 Subject: ARM: allow cortex-m0 to use hint instructions The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 458254e..9712ed3 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -271,23 +271,23 @@ class T1SystemEncoding opc> def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, T1SystemEncoding<0x00>, // A8.6.110 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, T1SystemEncoding<0x10>, // A8.6.410 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, T1SystemEncoding<0x20>, // A8.6.408 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, T1SystemEncoding<0x30>, // A8.6.409 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, T1SystemEncoding<0x40>, // A8.6.157 - Requires<[IsThumb2]>; + Requires<[IsThumb, HasV6M]>; def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>, T1SystemEncoding<0x50>, -- cgit v1.1 From 485333df7157d6e8681d910d85b271b0bc96b48e Mon Sep 17 00:00:00 2001 From: Richard Barton Date: Fri, 18 Oct 2013 14:09:49 +0000 Subject: Add hint disassembly syntax for 16-bit Thumb hint instructions. Patch by Artyom Skrobov git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192972 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 41 +++++++++++++++++++---------------------- 1 file changed, 19 insertions(+), 22 deletions(-) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 9712ed3..43dbd5c 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -269,30 +269,27 @@ class T1SystemEncoding opc> let Inst{7-0} = opc; } -def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, - T1SystemEncoding<0x00>, // A8.6.110 - Requires<[IsThumb, HasV6M]>; - -def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, - T1SystemEncoding<0x10>, // A8.6.410 - Requires<[IsThumb, HasV6M]>; - -def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, - T1SystemEncoding<0x20>, // A8.6.408 - Requires<[IsThumb, HasV6M]>; - -def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, - T1SystemEncoding<0x30>, // A8.6.409 - Requires<[IsThumb, HasV6M]>; - -def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, - T1SystemEncoding<0x40>, // A8.6.157 - Requires<[IsThumb, HasV6M]>; +def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", []>, + T1SystemEncoding<0x00>, + Requires<[IsThumb, HasV6M]> { + bits<4> imm; + let Inst{7-4} = imm; +} -def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>, - T1SystemEncoding<0x50>, - Requires<[IsThumb2, HasV8]>; +class tHintAlias : tInstAlias { + let Predicates = [IsThumb, HasV6M]; +} +def : tHintAlias<"hint$p $imm", (tHINT imm0_15:$imm, pred:$p)>; +def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110 +def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410 +def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408 +def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409 +def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157 +def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> { + let Predicates = [IsThumb2, HasV8]; +} +def : T2Pat<(int_arm_sevl), (tHINT 5)>; // The imm operand $val can be used by a debugger to store more information // about the breakpoint. -- cgit v1.1 From b161955ffbda5ccb5293e0c76ef982acb6ec6661 Mon Sep 17 00:00:00 2001 From: Artyom Skrobov Date: Wed, 23 Oct 2013 10:14:40 +0000 Subject: Make ARM hint ranges consistent, and add tests for these ranges git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193238 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrThumb.td | 1 - 1 file changed, 1 deletion(-) (limited to 'lib/Target/ARM/ARMInstrThumb.td') diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 43dbd5c..af5ef53 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -280,7 +280,6 @@ class tHintAlias : tInstAlias { let Predicates = [IsThumb, HasV6M]; } -def : tHintAlias<"hint$p $imm", (tHINT imm0_15:$imm, pred:$p)>; def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110 def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408 -- cgit v1.1