From 1f4abcfa5cf2a2d929d95714078ac16ebacba7d8 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Sat, 13 Nov 2010 10:43:34 +0000
Subject: Convert the modes to lower case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118998 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMInstrVFP.td | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'lib/Target/ARM/ARMInstrVFP.td')

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 046bed6..72ff723 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -76,7 +76,7 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
 
 multiclass vfp_ldst_d_mult<string asm, bit L_bit,
                            InstrItinClass itin, InstrItinClass itin_upd> {
-  def IA :
+  def ia :
     AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeNone, itin,
           !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -84,7 +84,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
     let Inst{21}    = 0;          // No writeback
     let Inst{20}    = L_bit;
   }
-  def IA_UPD :
+  def ia_UPD :
     AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeUpd, itin_upd,
           !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -92,7 +92,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
     let Inst{21}    = 1;          // Writeback
     let Inst{20}    = L_bit;
   }
-  def DB :
+  def db :
     AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeNone, itin,
           !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -100,7 +100,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
     let Inst{21}    = 0;          // No writeback
     let Inst{20}    = L_bit;
   }
-  def DB_UPD :
+  def db_UPD :
     AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeUpd, itin_upd,
           !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -112,7 +112,7 @@ multiclass vfp_ldst_d_mult<string asm, bit L_bit,
 
 multiclass vfp_ldst_s_mult<string asm, bit L_bit,
                            InstrItinClass itin, InstrItinClass itin_upd> {
-  def IA :
+  def ia :
     AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeNone, itin,
           !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -120,7 +120,7 @@ multiclass vfp_ldst_s_mult<string asm, bit L_bit,
     let Inst{21}    = 0;          // No writeback
     let Inst{20}    = L_bit;
   }
-  def IA_UPD :
+  def ia_UPD :
     AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeUpd, itin_upd,
           !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -128,7 +128,7 @@ multiclass vfp_ldst_s_mult<string asm, bit L_bit,
     let Inst{21}    = 1;          // Writeback
     let Inst{20}    = L_bit;
   }
-  def DB :
+  def db :
     AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeNone, itin,
           !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -136,7 +136,7 @@ multiclass vfp_ldst_s_mult<string asm, bit L_bit,
     let Inst{21}    = 0;          // No writeback
     let Inst{20}    = L_bit;
   }
-  def DB_UPD :
+  def db_UPD :
     AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
           IndexModeUpd, itin_upd,
           !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
-- 
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