From 33e57515b173baf572398fafeffcf4644c2a7381 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 10 Aug 2011 00:03:03 +0000 Subject: Push GPRnopc through a large number of instruction definitions to tighten operand decoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137189 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 59bed8d..acd1a41 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1177,10 +1177,10 @@ static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, if (pred == 0xF) return DecodeCPSInstruction(Inst, Insn, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rd, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rn, Address, Decoder); - DecodeGPRRegisterClass(Inst, Rm, Address, Decoder); - DecodeGPRRegisterClass(Inst, Ra, Address, Decoder); + DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder); + DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder); + DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder); + DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder); return true; } -- cgit v1.1