From a69da35c127dd7e35ae6216d965670643dc55bb6 Mon Sep 17 00:00:00 2001 From: Kevin Enderby Date: Wed, 11 Apr 2012 00:25:40 +0000 Subject: =?UTF-8?q?Fix=20ARM=20disassembly=20of=20VLD=20instructions=20wit?= =?UTF-8?q?h=20writebacks.=20=C2=A0And=20add=20test=20a=20case=20for=20all?= =?UTF-8?q?=20opcodes=20handed=20by=20DecodeVLDInstruction()=20in=20ARMDis?= =?UTF-8?q?assembler.cpp=20.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index dba5b6e..e1d63fa 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2262,6 +2262,8 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, case ARM::VLD2b8wb_register: case ARM::VLD2b16wb_register: case ARM::VLD2b32wb_register: + Inst.addOperand(MCOperand::CreateImm(0)); + break; case ARM::VLD3d8_UPD: case ARM::VLD3d16_UPD: case ARM::VLD3d32_UPD: @@ -2330,6 +2332,16 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; break; + case ARM::VLD2d8wb_fixed: + case ARM::VLD2d16wb_fixed: + case ARM::VLD2d32wb_fixed: + case ARM::VLD2b8wb_fixed: + case ARM::VLD2b16wb_fixed: + case ARM::VLD2b32wb_fixed: + case ARM::VLD2q8wb_fixed: + case ARM::VLD2q16wb_fixed: + case ARM::VLD2q32wb_fixed: + break; } return S; -- cgit v1.1