From a9611549fe5cd06000111851f88b951467695307 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Wed, 6 Apr 2011 18:27:46 +0000 Subject: Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 509a019..5ac0819 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -3037,7 +3037,7 @@ static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn, ElemSize esize = Opcode == ARM::VGETLNi32 ? ESize32 : ((Opcode == ARM::VGETLNs16 || Opcode == ARM::VGETLNu16) ? ESize16 - : ESize32); + : ESize8); // Rt = Inst{15-12} => ARM Rd MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, -- cgit v1.1