From dde038af59506c631ce181aff66e315a0c477f4d Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 20 Jul 2011 21:40:26 +0000 Subject: ARM PKH shift ammount operand printing tweaks. Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135626 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp') diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 320679e..22aa10c 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1632,16 +1632,11 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { // Extract the 5-bit immediate field Inst{11-7}. unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F; - ARM_AM::ShiftOpc Opc = ARM_AM::no_shift; - if (Opcode == ARM::PKHBT) - Opc = ARM_AM::lsl; - else if (Opcode == ARM::PKHTB) - Opc = ARM_AM::asr; - getImmShiftSE(Opc, ShiftAmt); if (Opcode == ARM::PKHBT || Opcode == ARM::PKHTB) MI.addOperand(MCOperand::CreateImm(ShiftAmt)); else - MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt))); + MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ARM_AM::no_shift, + ShiftAmt))); ++OpIdx; } -- cgit v1.1