From 80dd3e06129e2b570cbd65cba850571981df693a Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Tue, 30 Nov 2010 22:45:47 +0000 Subject: Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120481 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h') diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index eb92085..2c8345c 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1711,11 +1711,11 @@ static inline bool Thumb2PreloadOpcode(unsigned Opcode) { switch (Opcode) { default: return false; - case ARM::t2PLDi12: case ARM::t2PLDi8: case ARM::t2PLDpci: + case ARM::t2PLDi12: case ARM::t2PLDi8: case ARM::t2PLDs: - case ARM::t2PLDWi12: case ARM::t2PLDWi8: case ARM::t2PLDWpci: + case ARM::t2PLDWi12: case ARM::t2PLDWi8: case ARM::t2PLDWs: - case ARM::t2PLIi12: case ARM::t2PLIi8: case ARM::t2PLIpci: + case ARM::t2PLIi12: case ARM::t2PLIi8: case ARM::t2PLIs: return true; } @@ -1752,8 +1752,7 @@ static bool DisassembleThumb2PreLoad(MCInst &MI, unsigned Opcode, uint32_t insn, && !OpInfo[OpIdx].isOptionalDef() && "Pure imm operand expected"); int Offset = 0; - if (Opcode == ARM::t2PLDpci || Opcode == ARM::t2PLDWpci || - Opcode == ARM::t2PLIpci) { + if (slice(insn, 19, 16) == 0xFF) { bool Negative = slice(insn, 23, 23) == 0; unsigned Imm12 = getImm12(insn); Offset = Negative ? -1 - Imm12 : 1 * Imm12; -- cgit v1.1