From 61fda0d889b3578fe435455679182c231a649aac Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Fri, 25 Sep 2009 18:54:59 +0000 Subject: Rename getTargetNode to getMachineNode, for consistency with the naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp | 10 +++++----- lib/Target/Blackfin/BlackfinISelLowering.cpp | 24 ++++++++++++------------ 2 files changed, 17 insertions(+), 17 deletions(-) (limited to 'lib/Target/Blackfin') diff --git a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp index 28aeaed..fc62a18 100644 --- a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp +++ b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp @@ -177,11 +177,11 @@ void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) { // We cannot copy CC <-> !(CC/D) if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) { SDNode *Copy = - DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS, - NI->getDebugLoc(), - MVT::i32, - UI.getUse().get(), - DAG.getTargetConstant(BF::DRegClassID, MVT::i32)); + DAG.getMachineNode(TargetInstrInfo::COPY_TO_REGCLASS, + NI->getDebugLoc(), + MVT::i32, + UI.getUse().get(), + DAG.getTargetConstant(BF::DRegClassID, MVT::i32)); UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0)); } } diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 374ac27..4b321ec 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -422,26 +422,26 @@ SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) { unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB; // zext incoming carry flag in AC0 to 32 bits - SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32, - /* flag= */ Op.getOperand(2)); - CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, MVT::i32, - SDValue(CarryIn, 0)); + SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32, + /* flag= */ Op.getOperand(2)); + CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32, + SDValue(CarryIn, 0)); // Add operands, produce sum and carry flag - SDNode *Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, - Op.getOperand(0), Op.getOperand(1)); + SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag, + Op.getOperand(0), Op.getOperand(1)); // Store intermediate carry from Sum - SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32, - /* flag= */ SDValue(Sum, 1)); + SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32, + /* flag= */ SDValue(Sum, 1)); // Add incoming carry, again producing an output flag - Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, - SDValue(Sum, 0), SDValue(CarryIn, 0)); + Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Flag, + SDValue(Sum, 0), SDValue(CarryIn, 0)); // Update AC0 with the intermediate carry, producing a flag. - SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, MVT::Flag, - SDValue(Carry1, 0)); + SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Flag, + SDValue(Carry1, 0)); // Compose (i32, flag) pair SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) }; -- cgit v1.1