From f321e1075eabae96f62b1f2570d9dee5d10b8200 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Sat, 7 Jan 2012 19:42:13 +0000 Subject: Remove VectorExtras. This unused helper was written for a type of API that is discouraged now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147738 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelLowering.cpp | 1 - 1 file changed, 1 deletion(-) (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp') diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index dc0d5a6..2babc95 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -27,7 +27,6 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/ADT/VectorExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" -- cgit v1.1 From 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 Mon Sep 17 00:00:00 2001 From: David Blaikie Date: Fri, 20 Jan 2012 21:51:11 +0000 Subject: More dead code removal (using -Wunreachable-code) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelLowering.cpp | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp') diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 2babc95..191ba9c 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1038,7 +1038,6 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { llvm_unreachable("LowerConstantPool: Relocation model other than static" " not supported."); - return SDValue(); } //! Alternate entry point for generating the address of a constant pool entry @@ -1069,7 +1068,6 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { llvm_unreachable("LowerJumpTable: Relocation model other than static" " not supported."); - return SDValue(); } static SDValue @@ -1097,8 +1095,6 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { "not supported."); /*NOTREACHED*/ } - - return SDValue(); } //! Custom lower double precision floating point constants @@ -1696,7 +1692,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue T = DAG.getConstant(Value32, MVT::i32); return DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T)); - break; } case MVT::v2f64: { uint64_t f64val = uint64_t(SplatBits); @@ -1706,7 +1701,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue T = DAG.getConstant(f64val, MVT::i64); return DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T)); - break; } case MVT::v16i8: { // 8-bit constants have to be expanded to 16-bits @@ -1733,8 +1727,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl); } } - - return SDValue(); } /*! @@ -2008,8 +2000,6 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0); } } - - return SDValue(); } static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { @@ -2222,8 +2212,6 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, switch (Opc) { default: llvm_unreachable("Unhandled i8 math operator"); - /*NOTREACHED*/ - break; case ISD::ADD: { // 8-bit addition: Promote the arguments up to 16-bits and truncate // the result: @@ -2308,11 +2296,8 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, DAG.getNode(Opc, dl, MVT::i16, N0, N1)); - break; } } - - return SDValue(); } //! Lower byte immediate operations for v16i8 vectors: -- cgit v1.1 From bc2198133a1836598b54b943420748e75d5dea94 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 7 Feb 2012 02:50:20 +0000 Subject: Convert assert(0) to llvm_unreachable git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelLowering.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp') diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 191ba9c..4b57025 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -2033,8 +2033,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { int elt_byte = EltNo * VT.getSizeInBits() / 8; switch (VT.getSimpleVT().SimpleTy) { - default: - assert(false && "Invalid value type!"); + default: llvm_unreachable("Invalid value type!"); case MVT::i8: { prefslot_begin = prefslot_end = 3; break; @@ -2362,8 +2361,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (VT.getSimpleVT().SimpleTy) { - default: - assert(false && "Invalid value type!"); + default: llvm_unreachable("Invalid value type!"); case MVT::i8: { SDValue N = Op.getOperand(0); SDValue Elt0 = DAG.getConstant(0, MVT::i32); -- cgit v1.1 From ec52aaa12f57896fc806e849fa21a61603050ac4 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 28 Feb 2012 06:42:03 +0000 Subject: Some ARM implementaions, e.g. A-series, does return stack prediction. That is, the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelLowering.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp') diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 4b57025..3d2b32d 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -83,8 +83,9 @@ namespace { Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext()); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - 0, TLI.getLibcallCallingConv(LC), false, - /*isReturnValueUsed=*/true, + 0, TLI.getLibcallCallingConv(LC), + /*isTailCall=*/false, + /*doesNotRet=*/false, /*isReturnValueUsed=*/true, Callee, Args, DAG, Op.getDebugLoc()); return CallInfo.first; @@ -1274,7 +1275,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { SDValue SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, -- cgit v1.1 From 20bd5296cec8d8d597ab9db2aca7346a88e580c8 Mon Sep 17 00:00:00 2001 From: Daniel Dunbar Date: Tue, 28 Feb 2012 15:36:07 +0000 Subject: Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelLowering.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp') diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 3d2b32d..4b57025 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -83,9 +83,8 @@ namespace { Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext()); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - 0, TLI.getLibcallCallingConv(LC), - /*isTailCall=*/false, - /*doesNotRet=*/false, /*isReturnValueUsed=*/true, + 0, TLI.getLibcallCallingConv(LC), false, + /*isReturnValueUsed=*/true, Callee, Args, DAG, Op.getDebugLoc()); return CallInfo.first; @@ -1275,7 +1274,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { SDValue SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool doesNotRet, bool &isTailCall, + bool &isTailCall, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, -- cgit v1.1 From 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Tue, 28 Feb 2012 18:51:51 +0000 Subject: Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/CellSPU/SPUISelLowering.cpp | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp') diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 4b57025..3d2b32d 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -83,8 +83,9 @@ namespace { Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext()); std::pair CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - 0, TLI.getLibcallCallingConv(LC), false, - /*isReturnValueUsed=*/true, + 0, TLI.getLibcallCallingConv(LC), + /*isTailCall=*/false, + /*doesNotRet=*/false, /*isReturnValueUsed=*/true, Callee, Args, DAG, Op.getDebugLoc()); return CallInfo.first; @@ -1274,7 +1275,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { SDValue SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SmallVectorImpl &Ins, -- cgit v1.1