From 79698f60c4693ba305ba994b8349a3f6a6d6031e Mon Sep 17 00:00:00 2001
From: Scott Michel <scottm@aero.org>
Date: Thu, 20 Mar 2008 00:51:36 +0000
Subject: Add more patterns to match in the integer comparison test harnesses.
 Fix bugs encountered, mostly due to range matching for immediates; the
 CellSPU's 10-bit immediates are sign extended, covering a larger range of
 unsigned values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48575 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 4 ++--
 lib/Target/CellSPU/SPUInstrInfo.td     | 8 ++++----
 lib/Target/CellSPU/SPUOperands.td      | 5 ++---
 3 files changed, 8 insertions(+), 9 deletions(-)

(limited to 'lib/Target/CellSPU')

diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 1d4b28b..b81f277 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -65,14 +65,14 @@ namespace {
   bool
   isI32IntU10Immediate(ConstantSDNode *CN)
   {
-    return isU10Constant((int) CN->getValue());
+    return isU10Constant(CN->getSignExtended());
   }
 
   //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
   bool
   isI16IntS10Immediate(ConstantSDNode *CN)
   {
-    return isS10Constant((short) CN->getValue());
+    return isS10Constant(CN->getSignExtended());
   }
 
   //! SDNode predicate for i16 sign-extended, 10-bit immediate values
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index bd288d3..03efdc8 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -2708,7 +2708,7 @@ multiclass CmpGtrByteImm
                                                v16i8SExt8Imm:$val))]>;
   def r8:
     CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
-             [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
+              [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
 }
 
 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
@@ -2962,14 +2962,14 @@ def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
                     CLGTHIr16, CEQHIr16>;
 def : Pat<(setule R16C:$rA, R16C:$rB),
           (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
-def :  Pat<(setule R16C:$rA, i16ImmUns10:$imm),
+def :  Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
            (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
 
 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
-def : SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
+def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
                     ORr32, CLGTIr32, CEQIr32>;
 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
-def : SETCCBinOpImm<setult, R32C, immSExt8, i32, NORr32, CLGTIr32, CEQIr32>;
+def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
 def : Pat<(setule R32C:$rA, R32C:$rB),
           (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index da4b0f2..1e8eff5 100644
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -76,9 +76,8 @@ def uimm7: PatLeaf<(imm), [{
 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
 // field.
 def immSExt8  : PatLeaf<(imm), [{
-  int Value = (int) N->getValue();
-  int Value8 = (Value << 24) >> 24;
-  return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
+  int Value = int(N->getSignExtended());
+  return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
 }]>;
 
 // immU8: immediate, unsigned 8-bit quantity
-- 
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