From bc2198133a1836598b54b943420748e75d5dea94 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@gmail.com>
Date: Tue, 7 Feb 2012 02:50:20 +0000
Subject: Convert assert(0) to llvm_unreachable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/Hexagon/HexagonAsmPrinter.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'lib/Target/Hexagon/HexagonAsmPrinter.cpp')

diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index e2f7992..5402374 100644
--- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -318,14 +318,14 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
   if (Base.isReg())
     printOperand(MI, OpNo, O);
   else
-    assert(0 && "Unimplemented");
+    llvm_unreachable("Unimplemented");
 
   if (Offset.isImm()) {
     if (Offset.getImm())
       O << " + #" << Offset.getImm();
   }
   else
-    assert(0 && "Unimplemented");
+    llvm_unreachable("Unimplemented");
 
   return false;
 }
@@ -333,7 +333,7 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
 void HexagonAsmPrinter::printPredicateOperand(const MachineInstr *MI,
                                               unsigned OpNo,
                                               raw_ostream &O) {
-  assert(0 && "Unimplemented");
+  llvm_unreachable("Unimplemented");
 }
 
 
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