From 54a56fad36a32f12709da5f96998336f08524be9 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Fri, 7 Jun 2013 06:19:56 +0000 Subject: Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonCallingConvLower.h | 1 - 1 file changed, 1 deletion(-) (limited to 'lib/Target/Hexagon/HexagonCallingConvLower.h') diff --git a/lib/Target/Hexagon/HexagonCallingConvLower.h b/lib/Target/Hexagon/HexagonCallingConvLower.h index 489b3a3..eed99f4 100644 --- a/lib/Target/Hexagon/HexagonCallingConvLower.h +++ b/lib/Target/Hexagon/HexagonCallingConvLower.h @@ -48,7 +48,6 @@ class Hexagon_CCState { CallingConv::ID CallingConv; bool IsVarArg; const TargetMachine &TM; - const TargetRegisterInfo &TRI; SmallVector &Locs; LLVMContext &Context; -- cgit v1.1