From 99ad6ac65e8c97a0d3c9d884285dda01f793b7d1 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Thu, 2 May 2013 23:07:05 +0000 Subject: [mips] Handle reading, writing or copying of ccond field of DSP control register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsSEFrameLowering.cpp | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'lib/Target/Mips/MipsSEFrameLowering.cpp') diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index 2b76704..b295e91 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -40,6 +40,8 @@ public: private: bool expandInstr(MachineBasicBlock &MBB, Iter I); + void expandLoadCCond(MachineBasicBlock &MBB, Iter I); + void expandStoreCCond(MachineBasicBlock &MBB, Iter I); void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize); bool expandCopy(MachineBasicBlock &MBB, Iter I); @@ -71,6 +73,14 @@ bool ExpandPseudo::expand() { bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { switch(I->getOpcode()) { + case Mips::LOAD_CCOND_DSP: + case Mips::LOAD_CCOND_DSP_P8: + expandLoadCCond(MBB, I); + break; + case Mips::STORE_CCOND_DSP: + case Mips::STORE_CCOND_DSP_P8: + expandStoreCCond(MBB, I); + break; case Mips::LOAD_AC64: case Mips::LOAD_AC64_P8: case Mips::LOAD_AC_DSP: @@ -103,6 +113,36 @@ bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { return true; } +void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { + // load $vr, FI + // copy ccond, $vr + + assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); + + const TargetRegisterClass *RC = RegInfo.intRegClass(4); + unsigned VR = MRI.createVirtualRegister(RC); + unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); + + TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); + BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) + .addReg(VR, RegState::Kill); +} + +void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { + // copy $vr, ccond + // store $vr, FI + + assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); + + const TargetRegisterClass *RC = RegInfo.intRegClass(4); + unsigned VR = MRI.createVirtualRegister(RC); + unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); + + BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) + .addReg(Src, getKillRegState(I->getOperand(0).isKill())); + TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); +} + void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize) { // load $vr0, FI -- cgit v1.1 From d84ccfaf50c7843f31ffc74a8a8e33f779453d6e Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Sat, 11 May 2013 02:38:11 +0000 Subject: Change getFrameMoves to return a const reference. To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsSEFrameLowering.cpp | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'lib/Target/Mips/MipsSEFrameLowering.cpp') diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index b295e91..535c17c 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -262,7 +262,6 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { if (StackSize == 0 && !MFI->adjustsStack()) return; MachineModuleInfo &MMI = MF.getMMI(); - std::vector &Moves = MMI.getFrameMoves(); MachineLocation DstML, SrcML; // Adjust stack. @@ -274,7 +273,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); DstML = MachineLocation(MachineLocation::VirtualFP); SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); - Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML)); + MMI.addFrameMove(AdjustSPLabel, DstML, SrcML); const std::vector &CSI = MFI->getCalleeSavedInfo(); @@ -306,13 +305,13 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { if (!STI.isLittle()) std::swap(SrcML0, SrcML1); - Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0)); - Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1)); + MMI.addFrameMove(CSLabel, DstML0, SrcML0); + MMI.addFrameMove(CSLabel, DstML1, SrcML1); } else { // Reg is either in CPURegs or FGR32. DstML = MachineLocation(MachineLocation::VirtualFP, Offset); SrcML = MachineLocation(Reg); - Moves.push_back(MachineMove(CSLabel, DstML, SrcML)); + MMI.addFrameMove(CSLabel, DstML, SrcML); } } } @@ -337,7 +336,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I)); DstML = MachineLocation(MachineLocation::VirtualFP, Offset); SrcML = MachineLocation(ehDataReg(I)); - Moves.push_back(MachineMove(CSLabel2, DstML, SrcML)); + MMI.addFrameMove(CSLabel2, DstML, SrcML); } } @@ -352,7 +351,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); DstML = MachineLocation(FP); SrcML = MachineLocation(MachineLocation::VirtualFP); - Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML)); + MMI.addFrameMove(SetFPLabel, DstML, SrcML); } } -- cgit v1.1 From 6b67ffd68bb2e555b1b512a809f3c82c68f3debe Mon Sep 17 00:00:00 2001 From: Rafael Espindola Date: Thu, 16 May 2013 21:02:15 +0000 Subject: Remove addFrameMove. Now that we have good testing, remove addFrameMove and create cfi instructions directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182052 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsSEFrameLowering.cpp | 37 ++++++++++++++++----------------- 1 file changed, 18 insertions(+), 19 deletions(-) (limited to 'lib/Target/Mips/MipsSEFrameLowering.cpp') diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index 535c17c..fd6ac99 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -262,6 +262,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { if (StackSize == 0 && !MFI->adjustsStack()) return; MachineModuleInfo &MMI = MF.getMMI(); + const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo(); MachineLocation DstML, SrcML; // Adjust stack. @@ -271,9 +272,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel); - DstML = MachineLocation(MachineLocation::VirtualFP); - SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize); - MMI.addFrameMove(AdjustSPLabel, DstML, SrcML); + MMI.addFrameInst( + MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize)); const std::vector &CSI = MFI->getCalleeSavedInfo(); @@ -297,21 +297,22 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { // If Reg is a double precision register, emit two cfa_offsets, // one for each of the paired single precision registers. if (Mips::AFGR64RegClass.contains(Reg)) { - MachineLocation DstML0(MachineLocation::VirtualFP, Offset); - MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); - MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven)); - MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd)); + unsigned Reg0 = + MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpeven), true); + unsigned Reg1 = + MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpodd), true); if (!STI.isLittle()) - std::swap(SrcML0, SrcML1); + std::swap(Reg0, Reg1); - MMI.addFrameMove(CSLabel, DstML0, SrcML0); - MMI.addFrameMove(CSLabel, DstML1, SrcML1); + MMI.addFrameInst( + MCCFIInstruction::createOffset(CSLabel, Reg0, Offset)); + MMI.addFrameInst( + MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4)); } else { // Reg is either in CPURegs or FGR32. - DstML = MachineLocation(MachineLocation::VirtualFP, Offset); - SrcML = MachineLocation(Reg); - MMI.addFrameMove(CSLabel, DstML, SrcML); + MMI.addFrameInst(MCCFIInstruction::createOffset( + CSLabel, MRI.getDwarfRegNum(Reg, 1), Offset)); } } } @@ -334,9 +335,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2); for (int I = 0; I < 4; ++I) { int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I)); - DstML = MachineLocation(MachineLocation::VirtualFP, Offset); - SrcML = MachineLocation(ehDataReg(I)); - MMI.addFrameMove(CSLabel2, DstML, SrcML); + unsigned Reg = MRI.getDwarfRegNum(ehDataReg(I), true); + MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset)); } } @@ -349,9 +349,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel); - DstML = MachineLocation(FP); - SrcML = MachineLocation(MachineLocation::VirtualFP); - MMI.addFrameMove(SetFPLabel, DstML, SrcML); + MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( + SetFPLabel, MRI.getDwarfRegNum(FP, true))); } } -- cgit v1.1 From 41e632d9e1a55d36cb08b0551ad82a13d9137a5e Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Fri, 7 Jun 2013 07:04:14 +0000 Subject: Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsSEFrameLowering.cpp | 51 ++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 13 deletions(-) (limited to 'lib/Target/Mips/MipsSEFrameLowering.cpp') diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index fd6ac99..91ffb94 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -49,16 +49,12 @@ private: unsigned Src, unsigned RegSize); MachineFunction &MF; - const MipsSEInstrInfo &TII; - const MipsRegisterInfo &RegInfo; MachineRegisterInfo &MRI; }; } ExpandPseudo::ExpandPseudo(MachineFunction &MF_) - : MF(MF_), - TII(*static_cast(MF.getTarget().getInstrInfo())), - RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {} + : MF(MF_), MRI(MF.getRegInfo()) {} bool ExpandPseudo::expand() { bool Expanded = false; @@ -119,6 +115,11 @@ void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); + const MipsSEInstrInfo &TII = + *static_cast(MF.getTarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = + *static_cast(MF.getTarget().getRegisterInfo()); + const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); @@ -134,6 +135,11 @@ void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); + const MipsSEInstrInfo &TII = + *static_cast(MF.getTarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = + *static_cast(MF.getTarget().getRegisterInfo()); + const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex(); @@ -152,6 +158,11 @@ void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); + const MipsSEInstrInfo &TII = + *static_cast(MF.getTarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = + *static_cast(MF.getTarget().getRegisterInfo()); + const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); unsigned VR1 = MRI.createVirtualRegister(RC); @@ -176,6 +187,11 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); + const MipsSEInstrInfo &TII = + *static_cast(MF.getTarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = + *static_cast(MF.getTarget().getRegisterInfo()); + const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); unsigned VR1 = MRI.createVirtualRegister(RC); @@ -210,6 +226,11 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst, // copy $vr1, src_hi // copy dst_hi, $vr1 + const MipsSEInstrInfo &TII = + *static_cast(MF.getTarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = + *static_cast(MF.getTarget().getRegisterInfo()); + const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); unsigned VR1 = MRI.createVirtualRegister(RC); @@ -244,10 +265,12 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); - const MipsRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); + const MipsSEInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = + *static_cast(MF.getTarget().getRegisterInfo()); + MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; @@ -298,9 +321,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { // one for each of the paired single precision registers. if (Mips::AFGR64RegClass.contains(Reg)) { unsigned Reg0 = - MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpeven), true); + MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true); unsigned Reg1 = - MRI.getDwarfRegNum(RegInfo->getSubReg(Reg, Mips::sub_fpodd), true); + MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true); if (!STI.isLittle()) std::swap(Reg0, Reg1); @@ -326,7 +349,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { if (!MBB.isLiveIn(ehDataReg(I))) MBB.addLiveIn(ehDataReg(I)); TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false, - MipsFI->getEhDataRegFI(I), RC, RegInfo); + MipsFI->getEhDataRegFI(I), RC, &RegInfo); } // Emit .cfi_offset directives for eh data registers. @@ -359,10 +382,12 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); - const MipsRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); + const MipsSEInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = + *static_cast(MF.getTarget().getRegisterInfo()); + DebugLoc dl = MBBI->getDebugLoc(); unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; @@ -393,7 +418,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, // Insert instructions that restore eh data registers. for (int J = 0; J < 4; ++J) { TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J), - RC, RegInfo); + RC, &RegInfo); } } -- cgit v1.1