From 88d211f82304e53694ece666d4a2507b170e4582 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 12 Mar 2006 09:13:49 +0000 Subject: Several big changes: 1. Use flags on the instructions in the .td file to indicate the PPC970 unit type instead of a table in the .cpp file. Much cleaner. 2. Change the hazard recognizer to build d-groups according to the actual algorithm used, not my flawed understanding of it. 3. Model "must be in the first slot" and "must be the only instr in a group" accurately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPC.td | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'lib/Target/PowerPC/PPC.td') diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 272f6d6..d4d4995 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -67,17 +67,32 @@ def : Processor<"g5", G5Itineraries, Feature64Bit /*, Feature64BitRegs */]>; +def PPCInstrInfo : InstrInfo { + // Define how we want to layout our TargetSpecific information field... This + // should be kept up-to-date with the fields in the PPCInstrInfo.h file. + let TSFlagsFields = ["PPC970_First", + "PPC970_Single", + "PPC970_Unit"]; + let TSFlagsShifts = [0, + 1, + 2]; + + let isLittleEndianEncoding = 1; +} + + def PPC : Target { // Pointers on PPC are 32-bits in size. let PointerType = i32; + // Information about the instructions. + let InstructionSet = PPCInstrInfo; + + // According to the Mach-O Runtime ABI, these regs are nonvolatile across // calls let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15, F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31, CR2, CR3, CR4, LR]; - - // Pull in Instruction Info: - let InstructionSet = PowerPCInstrInfo; } -- cgit v1.1