From 0cfb42adb5072fb19a01dba3ea58a33fd5927947 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Fri, 15 Mar 2013 05:06:04 +0000 Subject: Allocate the RS spill slot for any PPC function with spills and a large stack frame For spills into a large stack frame, the FI-elimination code uses the register scavenger to obtain a free GPR for use with an r+r-addressed load or store. When there are no available GPRs, the scavenger gets one by using its spill slot. Previously, we were not always allocating that spill slot and the RS would assert when the spill slot was needed. I don't currently have a small test that triggered the assert, but I've created a small regression test that verifies that the spill slot is now added when the stack frame is sufficiently large. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCMachineFunctionInfo.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'lib/Target/PowerPC/PPCMachineFunctionInfo.h') diff --git a/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/lib/Target/PowerPC/PPCMachineFunctionInfo.h index 045b375..10b2160 100644 --- a/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ b/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -37,6 +37,9 @@ class PPCFunctionInfo : public MachineFunctionInfo { /// PEI. bool MustSaveLR; + /// Does this function have any stack spills. + bool HasSpills; + /// SpillsCR - Indicates whether CR is spilled in the current function. bool SpillsCR; @@ -78,6 +81,7 @@ public: explicit PPCFunctionInfo(MachineFunction &MF) : FramePointerSaveIndex(0), ReturnAddrSaveIndex(0), + HasSpills(false), SpillsCR(false), LRStoreRequired(false), MinReservedArea(0), @@ -109,6 +113,9 @@ public: void setMustSaveLR(bool U) { MustSaveLR = U; } bool mustSaveLR() const { return MustSaveLR; } + void setHasSpills() { HasSpills = true; } + bool hasSpills() const { return HasSpills; } + void setSpillsCR() { SpillsCR = true; } bool isCRSpilled() const { return SpillsCR; } -- cgit v1.1 From 324972904353594ad4a0cdfc79370f85e9fb9c8f Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sun, 17 Mar 2013 04:43:44 +0000 Subject: Improve PPC VR (Altivec) register spilling This change cleans up two issues with Altivec register spilling: 1. The spilling code was inefficient (using two instructions, and add and a load, when just one would do) 2. The code assumed that r0 would always be available (true for now, but this will change) The new code handles VR spilling just like GPR spills but forced into r+r mode. As a result, when any VR spills are present, we must now always allocate the register-scavenger spill slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCMachineFunctionInfo.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'lib/Target/PowerPC/PPCMachineFunctionInfo.h') diff --git a/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/lib/Target/PowerPC/PPCMachineFunctionInfo.h index 10b2160..b1636a2 100644 --- a/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ b/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -40,6 +40,10 @@ class PPCFunctionInfo : public MachineFunctionInfo { /// Does this function have any stack spills. bool HasSpills; + /// Does this function spill using instructions with only r+r (not r+i) + /// forms. + bool HasNonRISpills; + /// SpillsCR - Indicates whether CR is spilled in the current function. bool SpillsCR; @@ -82,6 +86,7 @@ public: : FramePointerSaveIndex(0), ReturnAddrSaveIndex(0), HasSpills(false), + HasNonRISpills(false), SpillsCR(false), LRStoreRequired(false), MinReservedArea(0), @@ -116,6 +121,9 @@ public: void setHasSpills() { HasSpills = true; } bool hasSpills() const { return HasSpills; } + void setHasNonRISpills() { HasNonRISpills = true; } + bool hasNonRISpills() const { return HasNonRISpills; } + void setSpillsCR() { SpillsCR = true; } bool isCRSpilled() const { return SpillsCR; } -- cgit v1.1