From 6a5339ba656805a9cd3bf7d884f99bb87ec84e98 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 14 Nov 2006 18:44:47 +0000 Subject: Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity, instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when the code is actually located above the 4G boundary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31734 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCRegisterInfo.td | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'lib/Target/PowerPC/PPCRegisterInfo.td') diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 07b022b..439650d 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -195,8 +195,13 @@ def CR7 : CR<7, "cr7">, DwarfRegNum<75>; // Link register def LR : SPR<8, "lr">, DwarfRegNum<65>; +//let Aliases = [LR] in +def LR8 : SPR<8, "lr">, DwarfRegNum<65>; + // Count register -def CTR : SPR<9, "ctr">, DwarfRegNum<66>; +def CTR : SPR<9, "ctr">, DwarfRegNum<66>; +def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>; + // VRsave register def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>; @@ -229,7 +234,7 @@ def GPRC : RegisterClass<"PPC", [i32], 32, def G8RC : RegisterClass<"PPC", [i64], 64, [X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17, - X16, X15, X14, X13, X31, X0, X1]> + X16, X15, X14, X13, X31, X0, X1, LR8]> { let MethodProtos = [{ iterator allocation_order_begin(const MachineFunction &MF) const; @@ -243,9 +248,9 @@ def G8RC : RegisterClass<"PPC", [i64], 64, G8RCClass::iterator G8RCClass::allocation_order_end(const MachineFunction &MF) const { if (hasFP(MF)) - return end()-3; + return end()-4; else - return end()-2; + return end()-3; } }]; } -- cgit v1.1