From efdd4673d6e78f3d406c5d1f44316aef8a5a9a48 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Thu, 28 Mar 2013 19:25:55 +0000 Subject: Add the PPC64 ldbrx/stdbrx instructions These are 64-bit load/store with byte-swap, and available on the P7 and the A2. Like the similar instructions for 16- and 32-bit words, these are matched in the target DAG-combine phase against load/store-bswap pairs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCSubtarget.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'lib/Target/PowerPC/PPCSubtarget.cpp') diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index 11b7fc2..be64700 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -41,6 +41,7 @@ PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, , HasSTFIWX(false) , HasISEL(false) , HasPOPCNTD(false) + , HasLDBRX(false) , IsBookE(false) , HasLazyResolverStubs(false) , IsJITCodeModel(false) -- cgit v1.1