From 928eb49cae286c95dceecf4442997dd561c6e3b7 Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Sun, 18 Apr 2010 20:31:01 +0000 Subject: Make processor FUs unique for given itinerary. This extends the limit of 32 FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCSchedule.td | 3 --- lib/Target/PowerPC/PPCScheduleG3.td | 3 ++- lib/Target/PowerPC/PPCScheduleG4.td | 3 ++- lib/Target/PowerPC/PPCScheduleG4Plus.td | 6 +++++- lib/Target/PowerPC/PPCScheduleG5.td | 3 ++- 5 files changed, 11 insertions(+), 7 deletions(-) (limited to 'lib/Target/PowerPC') diff --git a/lib/Target/PowerPC/PPCSchedule.td b/lib/Target/PowerPC/PPCSchedule.td index d589414..9664f14 100644 --- a/lib/Target/PowerPC/PPCSchedule.td +++ b/lib/Target/PowerPC/PPCSchedule.td @@ -15,8 +15,6 @@ def SLU : FuncUnit; // Store/load unit def SRU : FuncUnit; // special register unit def IU1 : FuncUnit; // integer unit 1 (simple) def IU2 : FuncUnit; // integer unit 2 (complex) -def IU3 : FuncUnit; // integer unit 3 (7450 simple) -def IU4 : FuncUnit; // integer unit 4 (7450 simple) def FPU1 : FuncUnit; // floating point unit 1 def FPU2 : FuncUnit; // floating point unit 2 def VPU : FuncUnit; // vector permutation unit @@ -24,7 +22,6 @@ def VIU1 : FuncUnit; // vector integer unit 1 (simple) def VIU2 : FuncUnit; // vector integer unit 2 (complex) def VFPU : FuncUnit; // vector floating point unit - //===----------------------------------------------------------------------===// // Instruction Itinerary classes used for PowerPC // diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td index f72194d..7344763 100644 --- a/lib/Target/PowerPC/PPCScheduleG3.td +++ b/lib/Target/PowerPC/PPCScheduleG3.td @@ -12,7 +12,8 @@ //===----------------------------------------------------------------------===// -def G3Itineraries : ProcessorItineraries<[ +def G3Itineraries : ProcessorItineraries< + [IU1, IU2, FPU1, BPU, SRU, SLU], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td index 92ed20f..7efc693 100644 --- a/lib/Target/PowerPC/PPCScheduleG4.td +++ b/lib/Target/PowerPC/PPCScheduleG4.td @@ -11,7 +11,8 @@ // //===----------------------------------------------------------------------===// -def G4Itineraries : ProcessorItineraries<[ +def G4Itineraries : ProcessorItineraries< + [IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, diff --git a/lib/Target/PowerPC/PPCScheduleG4Plus.td b/lib/Target/PowerPC/PPCScheduleG4Plus.td index 7474ba4..15056c0 100644 --- a/lib/Target/PowerPC/PPCScheduleG4Plus.td +++ b/lib/Target/PowerPC/PPCScheduleG4Plus.td @@ -11,7 +11,11 @@ // //===----------------------------------------------------------------------===// -def G4PlusItineraries : ProcessorItineraries<[ +def IU3 : FuncUnit; // integer unit 3 (7450 simple) +def IU4 : FuncUnit; // integer unit 4 (7450 simple) + +def G4PlusItineraries : ProcessorItineraries< + [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td index d282147..2dffc48 100644 --- a/lib/Target/PowerPC/PPCScheduleG5.td +++ b/lib/Target/PowerPC/PPCScheduleG5.td @@ -11,7 +11,8 @@ // //===----------------------------------------------------------------------===// -def G5Itineraries : ProcessorItineraries<[ +def G5Itineraries : ProcessorItineraries< + [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [ InstrItinData]>, InstrItinData]>, InstrItinData]>, -- cgit v1.1