From 36b56886974eae4f9c5ebc96befd3e7bfe5de338 Mon Sep 17 00:00:00 2001 From: Stephen Hines Date: Wed, 23 Apr 2014 16:57:46 -0700 Subject: Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617 --- lib/Target/R600/AMDILCFGStructurizer.cpp | 63 ++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 27 deletions(-) (limited to 'lib/Target/R600/AMDILCFGStructurizer.cpp') diff --git a/lib/Target/R600/AMDILCFGStructurizer.cpp b/lib/Target/R600/AMDILCFGStructurizer.cpp index 507570f..21ca560 100644 --- a/lib/Target/R600/AMDILCFGStructurizer.cpp +++ b/lib/Target/R600/AMDILCFGStructurizer.cpp @@ -13,14 +13,10 @@ #include "AMDGPU.h" #include "AMDGPUInstrInfo.h" #include "R600InstrInfo.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/SCCIterator.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" -#include "llvm/ADT/DepthFirstIterator.h" -#include "llvm/Analysis/DominatorInternals.h" -#include "llvm/Analysis/Dominators.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" @@ -30,6 +26,9 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachinePostDominators.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/IR/Dominators.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" @@ -54,6 +53,10 @@ STATISTIC(numLoopcontPatternMatch, "CFGStructurizer number of loop-continue " STATISTIC(numClonedBlock, "CFGStructurizer cloned blocks"); STATISTIC(numClonedInstr, "CFGStructurizer cloned instructions"); +namespace llvm { + void initializeAMDGPUCFGStructurizerPass(PassRegistry&); +} + //===----------------------------------------------------------------------===// // // Miscellaneous utility for CFGStructurizer. @@ -131,13 +134,13 @@ public: static char ID; - AMDGPUCFGStructurizer(TargetMachine &tm) : - MachineFunctionPass(ID), TM(tm), - TII(static_cast(tm.getInstrInfo())), - TRI(&TII->getRegisterInfo()) { } + AMDGPUCFGStructurizer() : + MachineFunctionPass(ID), TII(NULL), TRI(NULL) { + initializeAMDGPUCFGStructurizerPass(*PassRegistry::getPassRegistry()); + } const char *getPassName() const { - return "AMD IL Control Flow Graph structurizer Pass"; + return "AMDGPU Control Flow Graph structurizer Pass"; } void getAnalysisUsage(AnalysisUsage &AU) const { @@ -157,6 +160,8 @@ public: bool prepare(); bool runOnMachineFunction(MachineFunction &MF) { + TII = static_cast(MF.getTarget().getInstrInfo()); + TRI = &TII->getRegisterInfo(); DEBUG(MF.dump();); OrderedBlks.clear(); FuncRep = &MF; @@ -173,7 +178,6 @@ public: } protected: - TargetMachine &TM; MachineDominatorTree *MDT; MachinePostDominatorTree *PDT; MachineLoopInfo *MLI; @@ -220,7 +224,7 @@ protected: /// Compute the reversed DFS post order of Blocks void orderBlocks(MachineFunction *MF); - // Function originaly from CFGStructTraits + // Function originally from CFGStructTraits void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, DebugLoc DL = DebugLoc()); MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, @@ -786,7 +790,7 @@ bool AMDGPUCFGStructurizer::prepare() { bool AMDGPUCFGStructurizer::run() { //Assume reducible CFG... - DEBUG(dbgs() << "AMDGPUCFGStructurizer::run\n";FuncRep->viewCFG();); + DEBUG(dbgs() << "AMDGPUCFGStructurizer::run\n"); #ifdef STRESSTEST //Use the worse block ordering to test the algorithm. @@ -858,8 +862,7 @@ bool AMDGPUCFGStructurizer::run() { ContNextScc = false; DEBUG( dbgs() << "repeat processing SCC" << getSCCNum(MBB) - << "sccNumIter = " << SccNumIter << "\n"; - FuncRep->viewCFG(); + << "sccNumIter = " << SccNumIter << '\n'; ); } else { // Finish the current scc. @@ -915,12 +918,10 @@ bool AMDGPUCFGStructurizer::run() { BlockInfoMap.clear(); LLInfoMap.clear(); - DEBUG( - FuncRep->viewCFG(); - ); - - if (!Finish) - llvm_unreachable("IRREDUCIBL_CF"); + if (!Finish) { + DEBUG(FuncRep->viewCFG()); + llvm_unreachable("IRREDUCIBLE_CFG"); + } return true; } @@ -930,8 +931,8 @@ bool AMDGPUCFGStructurizer::run() { void AMDGPUCFGStructurizer::orderBlocks(MachineFunction *MF) { int SccNum = 0; MachineBasicBlock *MBB; - for (scc_iterator It = scc_begin(MF), E = scc_end(MF); - It != E; ++It, ++SccNum) { + for (scc_iterator It = scc_begin(MF); !It.isAtEnd(); + ++It, ++SccNum) { std::vector &SccNext = *It; for (std::vector::const_iterator blockIter = SccNext.begin(), blockEnd = SccNext.end(); @@ -1234,7 +1235,7 @@ int AMDGPUCFGStructurizer::handleJumpintoIfImp(MachineBasicBlock *HeadMBB, numClonedBlock += Num; Num += serialPatternMatch(*HeadMBB->succ_begin()); - Num += serialPatternMatch(*llvm::next(HeadMBB->succ_begin())); + Num += serialPatternMatch(*std::next(HeadMBB->succ_begin())); Num += ifPatternMatch(HeadMBB); assert(Num > 0); @@ -1763,7 +1764,7 @@ void AMDGPUCFGStructurizer::removeRedundantConditionalBranch( if (MBB->succ_size() != 2) return; MachineBasicBlock *MBB1 = *MBB->succ_begin(); - MachineBasicBlock *MBB2 = *llvm::next(MBB->succ_begin()); + MachineBasicBlock *MBB2 = *std::next(MBB->succ_begin()); if (MBB1 != MBB2) return; @@ -1899,6 +1900,14 @@ char AMDGPUCFGStructurizer::ID = 0; } // end anonymous namespace -FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm) { - return new AMDGPUCFGStructurizer(tm); +INITIALIZE_PASS_BEGIN(AMDGPUCFGStructurizer, "amdgpustructurizer", + "AMDGPU CFG Structurizer", false, false) +INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree) +INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) +INITIALIZE_PASS_END(AMDGPUCFGStructurizer, "amdgpustructurizer", + "AMDGPU CFG Structurizer", false, false) + +FunctionPass *llvm::createAMDGPUCFGStructurizerPass() { + return new AMDGPUCFGStructurizer(); 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