From 6a45d681e53a99b4c4f63e0b1664626a596a8151 Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 26 May 2010 00:28:19 +0000 Subject: Replace the SubRegSet tablegen class with a less error-prone mechanism. A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Sparc/SparcRegisterInfo.td | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'lib/Target/Sparc') diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index 2b05c19..fede929 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -20,6 +20,11 @@ class SparcCtrlReg: Register { let Namespace = "SP"; } +let Namespace = "SP" in { +def sub_even : SubRegIndex; +def sub_odd : SubRegIndex; +} + // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers class Ri num, string n> : SparcReg { @@ -33,6 +38,7 @@ class Rf num, string n> : SparcReg { class Rd num, string n, list subregs> : SparcReg { let Num = num; let SubRegs = subregs; + let SubRegIndices = [sub_even, sub_odd]; } // Control Registers -- cgit v1.1