From 5753f47f5bc965ec6a891a768dc7f1a26d655ac8 Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 14:24:01 +0000
Subject: Loads are not two-address in any way

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76033 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/SystemZ/SystemZInstrFP.td | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

(limited to 'lib/Target/SystemZ/SystemZInstrFP.td')

diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td
index d259ed4..202684f 100644
--- a/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/lib/Target/SystemZ/SystemZInstrFP.td
@@ -78,29 +78,28 @@ def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
                        "lcdbr\t{$dst, $src}",
                        [(set FP64:$dst, (fneg FP64:$src)),
                         (implicit PSW)]>;
-}
-
-let isTwoAddress = 1 in {
-let Defs = [PSW] in {
 
 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
-                       "lpebr\t{$dst}",
+                       "lpebr\t{$dst, $src}",
                        [(set FP32:$dst, (fabs FP32:$src)),
                         (implicit PSW)]>;
 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
-                       "lpdbr\t{$dst}",
+                       "lpdbr\t{$dst, $src}",
                        [(set FP64:$dst, (fabs FP64:$src)),
                         (implicit PSW)]>;
 
 def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
-                       "lnebr\t{$dst}",
+                       "lnebr\t{$dst, $src}",
                        [(set FP32:$dst, (fneg(fabs FP32:$src))),
                         (implicit PSW)]>;
 def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
-                       "lndbr\t{$dst}",
+                       "lndbr\t{$dst, $src}",
                        [(set FP64:$dst, (fneg(fabs FP64:$src))),
                         (implicit PSW)]>;
+}
 
+let isTwoAddress = 1 in {
+let Defs = [PSW] in {
 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
                        "aebr\t{$dst, $src2}",
-- 
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