From e09bcad77c033392669b8d9cd3d93209064dfbc4 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 30 Sep 2013 10:50:33 +0000 Subject: [SystemZ] Add definitions of LFH and STFH git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191661 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZInstrInfo.td | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'lib/Target/SystemZ') diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 4cd0875..b93e863 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -294,6 +294,8 @@ let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1, // Register loads. let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; + def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, + Requires<[FeatureHighWord]>; def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; // These instructions are split after register allocation, so we don't @@ -326,6 +328,8 @@ let Uses = [CC] in { // Register stores. let SimpleBDXStore = 1 in { defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; + def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, + Requires<[FeatureHighWord]>; def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; // These instructions are split after register allocation, so we don't -- cgit v1.1