From ebdeeab812beec0385b445f3d4c41a114e0d972f Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 8 Jul 2011 01:53:10 +0000 Subject: Eliminate asm parser's dependency on TargetMachine: - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h') diff --git a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h index 17c9052..5294a4f 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ b/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -17,6 +17,7 @@ #include namespace llvm { +class MCSubtargetInfo; class Target; class StringRef; @@ -31,9 +32,17 @@ namespace X86_MC { unsigned *rEBX, unsigned *rECX, unsigned *rEDX); void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model); + + /// createARMMCSubtargetInfo - Create a X86 MCSubtargetInfo instance. + /// This is exposed so Asm parser, etc. do not need to go through + /// TargetRegistry. + MCSubtargetInfo *createX86MCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS); } + } // End llvm namespace + // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // -- cgit v1.1