From a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4 Mon Sep 17 00:00:00 2001 From: Jim Laskey Date: Tue, 28 Mar 2006 13:48:33 +0000 Subject: Expose base register for DwarfWriter. Refactor code accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27225 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/X86RegisterInfo.cpp | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'lib/Target/X86/X86RegisterInfo.cpp') diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 99e36eb..97d73cf 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -686,15 +686,8 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, } } -void X86RegisterInfo::getLocation(MachineFunction &MF, unsigned Index, - MachineLocation &ML) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - bool FP = hasFP(MF); - - // FIXME - Needs to handle register variables. - // FIXME - Hardcoding gcc numbering. - ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP), - MFI->getObjectOffset(Index) + MFI->getStackSize()); +unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const { + return getDwarfRegNum(hasFP(MF) ? X86::EBP : X86::ESP); } #include "X86GenRegisterInfo.inc" -- cgit v1.1