From 881e3cca66c64a57ff431a4f6d1136dd6017c137 Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Sun, 16 Dec 2012 17:29:14 +0000 Subject: Add XCore disassembler. Currently there is no instruction encoding info and XCoreDisassembler::getInstruction() always returns Fail. I intend to add instruction encodings and tests in follow on commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../XCore/Disassembler/XCoreDisassembler.cpp | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 lib/Target/XCore/Disassembler/XCoreDisassembler.cpp (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp') diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp new file mode 100644 index 0000000..16b3c20 --- /dev/null +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -0,0 +1,68 @@ +//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file is part of the XCore Disassembler. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/MemoryObject.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +typedef MCDisassembler::DecodeStatus DecodeStatus; + +namespace { + +/// XCoreDisassembler - a disasembler class for XCore. +class XCoreDisassembler : public MCDisassembler { +public: + /// Constructor - Initializes the disassembler. + /// + XCoreDisassembler(const MCSubtargetInfo &STI) : + MCDisassembler(STI) {} + + /// getInstruction - See MCDisassembler. + virtual DecodeStatus getInstruction(MCInst &instr, + uint64_t &size, + const MemoryObject ®ion, + uint64_t address, + raw_ostream &vStream, + raw_ostream &cStream) const; +}; + +} + +MCDisassembler::DecodeStatus +XCoreDisassembler::getInstruction(MCInst &instr, + uint64_t &Size, + const MemoryObject &Region, + uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const { + return Fail; +} + +namespace llvm { + extern Target TheXCoreTarget; +} + +static MCDisassembler *createXCoreDisassembler(const Target &T, + const MCSubtargetInfo &STI) { + return new XCoreDisassembler(STI); +} + +extern "C" void LLVMInitializeXCoreDisassembler() { + // Register the disassembler. + TargetRegistry::RegisterMCDisassembler(TheXCoreTarget, + createXCoreDisassembler); +} -- cgit v1.1 From 54d6266e9baa8c2796c4a95c35897b5c67d8d910 Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Sun, 16 Dec 2012 17:37:34 +0000 Subject: Add instruction encodings and disassembly for 1r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../XCore/Disassembler/XCoreDisassembler.cpp | 66 +++++++++++++++++++++- 1 file changed, 63 insertions(+), 3 deletions(-) (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp') diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 16b3c20..d0a98d13 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -11,8 +11,11 @@ // //===----------------------------------------------------------------------===// +#include "XCore.h" +#include "XCoreRegisterInfo.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/MemoryObject.h" #include "llvm/Support/TargetRegistry.h" @@ -25,11 +28,12 @@ namespace { /// XCoreDisassembler - a disasembler class for XCore. class XCoreDisassembler : public MCDisassembler { + const MCRegisterInfo *RegInfo; public: /// Constructor - Initializes the disassembler. /// - XCoreDisassembler(const MCSubtargetInfo &STI) : - MCDisassembler(STI) {} + XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) : + MCDisassembler(STI), RegInfo(Info) {} /// getInstruction - See MCDisassembler. virtual DecodeStatus getInstruction(MCInst &instr, @@ -38,8 +42,50 @@ public: uint64_t address, raw_ostream &vStream, raw_ostream &cStream) const; + + const MCRegisterInfo *getRegInfo() const { return RegInfo; } }; +} +static bool readInstruction16(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint16_t &insn) { + uint8_t Bytes[4]; + + // We want to read exactly 2 Bytes of data. + if (region.readBytes(address, 2, Bytes, NULL) == -1) { + size = 0; + return false; + } + // Encoded as a little-endian 16-bit word in the stream. + insn = (Bytes[0] << 0) | (Bytes[1] << 8); + return true; +} + +static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { + const XCoreDisassembler *Dis = static_cast(D); + return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); +} + + +static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +#include "XCoreGenDisassemblerTables.inc" + +static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) +{ + if (RegNo > 11) + return MCDisassembler::Fail; + unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); + Inst.addOperand(MCOperand::CreateReg(Reg)); + return MCDisassembler::Success; } MCDisassembler::DecodeStatus @@ -49,6 +95,20 @@ XCoreDisassembler::getInstruction(MCInst &instr, uint64_t Address, raw_ostream &vStream, raw_ostream &cStream) const { + uint16_t low; + + if (!readInstruction16(Region, Address, Size, low)) { + return Fail; + } + + // Calling the auto-generated decoder function. + DecodeStatus Result = decodeInstruction(DecoderTable16, instr, low, Address, + this, STI); + if (Result != Fail) { + Size = 2; + return Result; + } + return Fail; } @@ -58,7 +118,7 @@ namespace llvm { static MCDisassembler *createXCoreDisassembler(const Target &T, const MCSubtargetInfo &STI) { - return new XCoreDisassembler(STI); + return new XCoreDisassembler(STI, T.createMCRegInfo("")); } extern "C" void LLVMInitializeXCoreDisassembler() { -- cgit v1.1 From b4d40a04f0639fdec8329a8708565411fa53b5bc Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Mon, 17 Dec 2012 12:13:41 +0000 Subject: Update comments to match recommended doxygen style. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp') diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index d0a98d13..16b91d9 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -6,9 +6,10 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -// -// This file is part of the XCore Disassembler. -// +/// +/// \file +/// \brief This file is part of the XCore Disassembler. +/// //===----------------------------------------------------------------------===// #include "XCore.h" @@ -26,16 +27,14 @@ typedef MCDisassembler::DecodeStatus DecodeStatus; namespace { -/// XCoreDisassembler - a disasembler class for XCore. +/// \brief A disassembler class for XCore. class XCoreDisassembler : public MCDisassembler { const MCRegisterInfo *RegInfo; public: - /// Constructor - Initializes the disassembler. - /// XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) : MCDisassembler(STI), RegInfo(Info) {} - /// getInstruction - See MCDisassembler. + /// \brief See MCDisassembler. virtual DecodeStatus getInstruction(MCInst &instr, uint64_t &size, const MemoryObject ®ion, -- cgit v1.1 From 1ffe48a84b398e8cebbdc7a47bedb57e1e67e63f Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Mon, 17 Dec 2012 12:29:31 +0000 Subject: Add instruction encodings / disassembly support for 2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../XCore/Disassembler/XCoreDisassembler.cpp | 67 +++++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp') diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 16b91d9..4257944 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -67,12 +67,26 @@ static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); } - static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus Decode2RInstruction(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeR2RInstruction(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + +static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -87,6 +101,57 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus +Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { + unsigned Combined = fieldFromInstruction(Insn, 6, 5) + + fieldFromInstruction(Insn, 5, 1) * 5 - 27; + if (Combined >= 9) + return MCDisassembler::Fail; + + unsigned Op1High = Combined % 3; + unsigned Op2High = Combined / 3; + Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2); + Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2); + return MCDisassembler::Success; +} + +static DecodeStatus +Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + } + return S; +} + +static DecodeStatus +Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + } + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, -- cgit v1.1 From 35150cbf4166ae8d69032d355f1e8d83b4a6eb3c Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Mon, 17 Dec 2012 13:50:04 +0000 Subject: Add instruction encodings / disassembly support for rus instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../XCore/Disassembler/XCoreDisassembler.cpp | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp') diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 4257944..ebbde96 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -72,6 +72,9 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -87,6 +90,21 @@ static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeRUSInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -101,6 +119,17 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + if (Val > 11) + return MCDisassembler::Fail; + static unsigned Values[] = { + 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32 + }; + Inst.addOperand(MCOperand::CreateImm(Values[Val])); + return MCDisassembler::Success; +} + static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { unsigned Combined = fieldFromInstruction(Insn, 6, 5) + @@ -152,6 +181,43 @@ Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } +static DecodeStatus +DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + Inst.addOperand(MCOperand::CreateImm(Op2)); + } + return S; +} + +static DecodeStatus +DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeBitpOperand(Inst, Op2, Address, Decoder); + } + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, -- cgit v1.1 From 6e43b7f6b20b39b041cf24d732ddb802bbd6471a Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Mon, 17 Dec 2012 13:55:49 +0000 Subject: Fix parameter name in prototypes in XCoreDisassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp') diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index ebbde96..4f60724 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -76,17 +76,17 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); static DecodeStatus Decode2RInstruction(MCInst &Inst, - unsigned RegNo, + unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeR2RInstruction(MCInst &Inst, - unsigned RegNo, + unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, - unsigned RegNo, + unsigned Insn, uint64_t Address, const void *Decoder); -- cgit v1.1 From c47793c62c434bd27fee1d243c2081a34d4f3817 Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Mon, 17 Dec 2012 16:28:02 +0000 Subject: Add instruction encodings / disassembly support for l2r instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../XCore/Disassembler/XCoreDisassembler.cpp | 74 ++++++++++++++++++++-- 1 file changed, 70 insertions(+), 4 deletions(-) (limited to 'lib/Target/XCore/Disassembler/XCoreDisassembler.cpp') diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index 4f60724..094f18c 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -62,6 +62,23 @@ static bool readInstruction16(const MemoryObject ®ion, return true; } +static bool readInstruction32(const MemoryObject ®ion, + uint64_t address, + uint64_t &size, + uint32_t &insn) { + uint8_t Bytes[4]; + + // We want to read exactly 4 Bytes of data. + if (region.readBytes(address, 4, Bytes, NULL) == -1) { + size = 0; + return false; + } + // Encoded as a little-endian 32-bit word in the stream. + insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | + (Bytes[3] << 24); + return true; +} + static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { const XCoreDisassembler *Dis = static_cast(D); return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); @@ -105,6 +122,16 @@ static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeL2RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -218,6 +245,32 @@ DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } +static DecodeStatus +DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), + Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + } + return S; +} + +static DecodeStatus +DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2; + DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16), + Op1, Op2); + if (S == MCDisassembler::Success) { + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + } + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, @@ -225,20 +278,33 @@ XCoreDisassembler::getInstruction(MCInst &instr, uint64_t Address, raw_ostream &vStream, raw_ostream &cStream) const { - uint16_t low; + uint16_t insn16; - if (!readInstruction16(Region, Address, Size, low)) { + if (!readInstruction16(Region, Address, Size, insn16)) { return Fail; } // Calling the auto-generated decoder function. - DecodeStatus Result = decodeInstruction(DecoderTable16, instr, low, Address, - this, STI); + DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16, + Address, this, STI); if (Result != Fail) { Size = 2; return Result; } + uint32_t insn32; + + if (!readInstruction32(Region, Address, Size, insn32)) { + return Fail; + } + + // Calling the auto-generated decoder function. + Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI); + if (Result != Fail) { + Size = 4; + return Result; + } + return Fail; } -- cgit v1.1