From 348da8d6b5e002c3698c37aca26c508bc60a05bb Mon Sep 17 00:00:00 2001 From: Matheus Almeida Date: Mon, 21 Oct 2013 13:07:13 +0000 Subject: [mips][msa] Direct Object Emission support for LD/ST instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 19 +++++++++ lib/Target/Mips/MipsMSAInstrFormats.td | 11 +++++ lib/Target/Mips/MipsMSAInstrInfo.td | 50 ++++++++++++----------- 3 files changed, 56 insertions(+), 24 deletions(-) (limited to 'lib/Target') diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index da49564..37ea382 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -210,6 +210,9 @@ static DecodeStatus DecodeMem(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); + static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -530,6 +533,22 @@ static DecodeStatus DecodeMem(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); + unsigned Reg = fieldFromInstruction(Insn, 6, 5); + unsigned Base = fieldFromInstruction(Insn, 11, 5); + + Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index bbb407a..1357deb 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -341,6 +341,17 @@ class MSA_I10_FMT major, bits<2> df, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_MI10_FMT df, bits<4> minor>: MSAInst { + bits<21> addr; + bits<5> wd; + + let Inst{25-16} = addr{9-0}; + let Inst{15-11} = addr{20-16}; + let Inst{10-6} = wd; + let Inst{5-2} = minor; + let Inst{1-0} = df; +} + class MSA_VEC_FMT major, bits<6> minor>: MSAInst { bits<5> wt; bits<5> ws; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 0199b8c..bddd6b1 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -758,10 +758,10 @@ class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; -class LD_B_ENC : MSA_I5_FMT<0b110, 0b00, 0b000111>; -class LD_H_ENC : MSA_I5_FMT<0b110, 0b01, 0b000111>; -class LD_W_ENC : MSA_I5_FMT<0b110, 0b10, 0b000111>; -class LD_D_ENC : MSA_I5_FMT<0b110, 0b11, 0b000111>; +class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; +class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; +class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; +class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; class LDI_B_ENC : MSA_I10_FMT<0b010, 0b00, 0b001100>; class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>; @@ -982,10 +982,10 @@ class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; -class ST_B_ENC : MSA_I5_FMT<0b111, 0b00, 0b000111>; -class ST_H_ENC : MSA_I5_FMT<0b111, 0b01, 0b000111>; -class ST_W_ENC : MSA_I5_FMT<0b111, 0b10, 0b000111>; -class ST_D_ENC : MSA_I5_FMT<0b111, 0b11, 0b000111>; +class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; +class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; +class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; +class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; @@ -2037,20 +2037,21 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d, MSA128DOpnd>; class LD_DESC_BASE { - dag OutOperandList = (outs RCWD:$wd); + dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addr); string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); - list Pattern = [(set RCWD:$wd, (TyNode (OpNode Addr:$addr)))]; + list Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; InstrItinClass Itinerary = itin; + string DecoderMethod = "DecodeMSA128Mem"; } -class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128B>; -class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128H>; -class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128W>; -class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128D>; +class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>; +class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>; +class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>; +class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>; class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; @@ -2364,20 +2365,21 @@ class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d, MSA128DOpnd>; class ST_DESC_BASE { dag OutOperandList = (outs); - dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr); + dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); - list Pattern = [(OpNode (TyNode RCWD:$wd), Addr:$addr)]; + list Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; InstrItinClass Itinerary = itin; + string DecoderMethod = "DecodeMSA128Mem"; } -class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128B>; -class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128H>; -class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128W>; -class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128D>; +class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>; +class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>; +class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>; +class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>; class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, MSA128BOpnd>; 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