From 7e2c793a2b5c746344652b6579e958ee42fafdcc Mon Sep 17 00:00:00 2001 From: Sylvestre Ledru Date: Thu, 27 Sep 2012 09:59:43 +0000 Subject: Fix a typo 'iff' => 'if' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMFastISel.cpp | 2 +- lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 +- lib/Target/ARM/ARMISelLowering.cpp | 8 ++++---- lib/Target/ARM/ARMInstrThumb.td | 2 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 +++--- lib/Target/MSP430/MSP430ISelDAGToDAG.cpp | 2 +- lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 +- lib/Target/X86/X86FloatingPoint.cpp | 2 +- lib/Target/X86/X86ISelDAGToDAG.cpp | 2 +- lib/Target/X86/X86InstrInfo.cpp | 2 +- lib/Target/XCore/XCoreISelLowering.cpp | 6 +++--- 11 files changed, 18 insertions(+), 18 deletions(-) (limited to 'lib/Target') diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 8933a02..1458e33 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -276,7 +276,7 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { if (TII.isPredicable(MI) || isARMNEONPred(MI)) AddDefaultPred(MIB); - // Do we optionally set a predicate? Preds is size > 0 iff the predicate + // Do we optionally set a predicate? Preds is size > 0 if the predicate // defines CPSR. All other OptionalDefines in ARM are the CCR register. bool CPSR = false; if (DefinesOptionalPredicate(MI, &CPSR)) { diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 1eea0cc..e9f0c8a 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -2117,7 +2117,7 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N, if (N->getOpcode() == ISD::AND) { if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) { - // The immediate is a mask of the low bits iff imm & (imm+1) == 0 + // The immediate is a mask of the low bits if imm & (imm+1) == 0 if (And_imm & (And_imm + 1)) return NULL; diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index f8455a4..33c4835 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -727,7 +727,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR - // iff target supports vfp2. + // if target supports vfp2. setOperationAction(ISD::BITCAST, MVT::i64, Custom); setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); } @@ -7692,12 +7692,12 @@ static SDValue PerformORCombine(SDNode *N, DebugLoc DL = N->getDebugLoc(); // 1) or (and A, mask), val => ARMbfi A, val, mask - // iff (val & mask) == val + // if (val & mask) == val // // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask - // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) + // 2a) if isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) // && mask == ~mask2 - // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) + // 2b) if isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) // && ~mask == mask2 // (i.e., copy a bitfield value into another bitfield of the same width) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index e171f8b..ca3d6d7 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -698,7 +698,7 @@ def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), } // Writeback version is just a pseudo, as there's no encoding difference. -// Writeback happens iff the base register is not in the destination register +// Writeback happens if the base register is not in the destination register // list. def tLDMIA_UPD : InstTemplate is specified and encoding T2 is preferred // to encoding T1 if is omitted." @@ -7033,7 +7033,7 @@ processInstruction(MCInst &Inst, } break; case ARM::tSUBi8: - // If the immediate is in the range 0-7, we want tADDi3 iff Rd was + // If the immediate is in the range 0-7, we want tADDi3 if Rd was // explicitly specified. From the ARM ARM: "Encoding T1 is preferred // to encoding T2 if is specified and encoding T2 is preferred // to encoding T1 if is omitted." diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 5efc6a3..e704548 100644 --- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -221,7 +221,7 @@ bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) { } case ISD::OR: - // Handle "X | C" as "X + C" iff X is known to have C bits clear. + // Handle "X | C" as "X + C" if X is known to have C bits clear. if (ConstantSDNode *CN = dyn_cast(N.getOperand(1))) { MSP430ISelAddressMode Backup = AM; uint64_t Offset = CN->getSExtValue(); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index e8f4d16..4f8aa4c 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -74,7 +74,7 @@ namespace { return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); } - /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s + /// isRunOfOnes - Returns true if Val consists of one contiguous run of 1s /// with any number of 0s on either side. The 1s are allowed to wrap from /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. /// 0x0F0F0000 is not, since all 1s are not contiguous. diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 791f598..2d027dd 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -1280,7 +1280,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { } /// handleCondMovFP - Handle two address conditional move instructions. These -/// instructions move a st(i) register to st(0) iff a condition is true. These +/// instructions move a st(i) register to st(0) if a condition is true. These /// instructions require that the first operand is at the top of the stack, but /// otherwise don't modify the stack at all. void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 40605af..81be243 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -1202,7 +1202,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, } case ISD::OR: - // Handle "X | C" as "X + C" iff X is known to have C bits clear. + // Handle "X | C" as "X + C" if X is known to have C bits clear. if (CurDAG->isBaseWithConstantOffset(N)) { X86ISelAddressMode Backup = AM; ConstantSDNode *CN = cast(N.getOperand(1)); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index f46989f..69c7c9a 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1652,7 +1652,7 @@ static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, Iter = I; for (unsigned i = 0; i < 4; ++i) { // If we make it to the beginning of the block, it's safe to clobber - // EFLAGS iff EFLAGS is not live-in. + // EFLAGS if EFLAGS is not live-in. if (Iter == B) return !MBB.isLiveIn(X86::EFLAGS); diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 3695ce2..8231d1b 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1361,7 +1361,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, return DAG.getMergeValues(Ops, 2, dl); } - // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the + // fold (ladd x, 0, y) -> 0, add x, y if carry is unused and y has only the // low bit set if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) { APInt KnownZero, KnownOne; @@ -1385,7 +1385,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, ConstantSDNode *N1C = dyn_cast(N1); EVT VT = N0.getValueType(); - // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set + // fold (lsub 0, 0, x) -> x, -x if x has only the low bit set if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { APInt KnownZero, KnownOne; APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), @@ -1400,7 +1400,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, } } - // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the + // fold (lsub x, 0, y) -> 0, sub x, y if borrow is unused and y has only the // low bit set if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) { APInt KnownZero, KnownOne; -- cgit v1.1