From a6c3a4ee76ef8464d3c83472e15af521ade7eeb4 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 28 Aug 2013 10:26:24 +0000 Subject: [mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189468 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrFormats.td | 5 ++++ lib/Target/Mips/MipsMSAInstrInfo.td | 24 +++++++++++++++++ lib/Target/Mips/MipsRegisterInfo.cpp | 10 +++++++ lib/Target/Mips/MipsRegisterInfo.td | 13 +++++++++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 48 ++++++++++++++++++++++++++++++++++ lib/Target/Mips/MipsSEISelDAGToDAG.h | 2 ++ lib/Target/Mips/MipsSEInstrInfo.cpp | 4 +++ 7 files changed, 106 insertions(+) (limited to 'lib/Target') diff --git a/lib/Target/Mips/MipsMSAInstrFormats.td b/lib/Target/Mips/MipsMSAInstrFormats.td index 35082c2..f337f9d 100644 --- a/lib/Target/Mips/MipsMSAInstrFormats.td +++ b/lib/Target/Mips/MipsMSAInstrFormats.td @@ -69,6 +69,11 @@ class MSA_3RF_FMT major, bits<1> df, bits<6> minor>: MSAInst { let Inst{5-0} = minor; } +class MSA_ELM_FMT major, bits<6> minor>: MSAInst { + let Inst{25-16} = major; + let Inst{5-0} = minor; +} + class MSA_ELM_B_FMT major, bits<6> minor>: MSAInst { let Inst{25-22} = major; let Inst{21-20} = 0b00; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index e7688ca..e53b29e 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -171,6 +171,8 @@ class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; +class CFCMSA_ENC : MSA_ELM_FMT<0b0001111110, 0b011001>; + class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; @@ -219,6 +221,8 @@ class COPY_U_B_ENC : MSA_ELM_B_FMT<0b0011, 0b011001>; class COPY_U_H_ENC : MSA_ELM_H_FMT<0b0011, 0b011001>; class COPY_U_W_ENC : MSA_ELM_W_FMT<0b0011, 0b011001>; +class CTCMSA_ENC : MSA_ELM_FMT<0b0000111110, 0b011001>; + class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; @@ -1155,6 +1159,14 @@ class CEQI_W_DESC : MSA_SI5_DESC_BASE<"ceqi.w", int_mips_ceqi_w, NoItinerary, class CEQI_D_DESC : MSA_SI5_DESC_BASE<"ceqi.d", int_mips_ceqi_d, NoItinerary, MSA128D, MSA128D>; +class CFCMSA_DESC { + dag OutOperandList = (outs GPR32:$rd); + dag InOperandList = (ins MSACtrl:$cs); + string AsmString = "cfcmsa\t$rd, $cs"; + InstrItinClass Itinerary = NoItinerary; + bit hasSideEffects = 1; +} + class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", int_mips_cle_s_b, NoItinerary, MSA128B, MSA128B>; class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", int_mips_cle_s_h, NoItinerary, @@ -1241,6 +1253,14 @@ class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", int_mips_copy_u_h, class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", int_mips_copy_u_w, NoItinerary, GPR32, MSA128W>; +class CTCMSA_DESC { + dag OutOperandList = (outs); + dag InOperandList = (ins MSACtrl:$cd, GPR32:$rs); + string AsmString = "ctcmsa\t$cd, $rs"; + InstrItinClass Itinerary = NoItinerary; + bit hasSideEffects = 1; +} + class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", int_mips_div_s_b, NoItinerary, MSA128B, MSA128B>; class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", int_mips_div_s_h, NoItinerary, @@ -2299,6 +2319,8 @@ def CEQI_H : CEQI_H_ENC, CEQI_H_DESC, Requires<[HasMSA]>; def CEQI_W : CEQI_W_ENC, CEQI_W_DESC, Requires<[HasMSA]>; def CEQI_D : CEQI_D_ENC, CEQI_D_DESC, Requires<[HasMSA]>; +def CFCMSA : CFCMSA_ENC, CFCMSA_DESC, Requires<[HasMSA]>; + def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC, Requires<[HasMSA]>; def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC, Requires<[HasMSA]>; def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC, Requires<[HasMSA]>; @@ -2347,6 +2369,8 @@ def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC, Requires<[HasMSA]>; def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC, Requires<[HasMSA]>; def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, Requires<[HasMSA]>; +def CTCMSA : CTCMSA_ENC, CTCMSA_DESC, Requires<[HasMSA]>; + def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC, Requires<[HasMSA]>; def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC, Requires<[HasMSA]>; def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC, Requires<[HasMSA]>; diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 03d09a6..ee81bae 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -167,6 +167,16 @@ getReservedRegs(const MachineFunction &MF) const { Reserved.set(Mips::DSPEFI); Reserved.set(Mips::DSPOutFlag); + // Reserve MSA control registers. + Reserved.set(Mips::MSAIR); + Reserved.set(Mips::MSACSR); + Reserved.set(Mips::MSAAccess); + Reserved.set(Mips::MSASave); + Reserved.set(Mips::MSAModify); + Reserved.set(Mips::MSARequest); + Reserved.set(Mips::MSAMap); + Reserved.set(Mips::MSAUnmap); + // Reserve RA if in mips16 mode. if (Subtarget.inMips16Mode()) { Reserved.set(Mips::RA); diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 22c4890..cef5ebf 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -231,6 +231,16 @@ let Namespace = "Mips" in { def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, DSPOutFlag21, DSPOutFlag22, DSPOutFlag23]>; + + // MSA-ASE control registers. + def MSAIR : Register<"0">; + def MSACSR : Register<"1">; + def MSAAccess : Register<"2">; + def MSASave : Register<"3">; + def MSAModify : Register<"4">; + def MSARequest : Register<"5">; + def MSAMap : Register<"6">; + def MSAUnmap : Register<"7">; } //===----------------------------------------------------------------------===// @@ -329,6 +339,9 @@ def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, (sequence "W%u", 0, 31)>; +def MSACtrl: RegisterClass<"Mips", [i32], 32, (add + MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; + // Hi/Lo Registers def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 203196e..221aeda 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -66,6 +66,21 @@ void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, MIB.addReg(Mips::DSPEFI, Flag); } +unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { + switch (cast(RegIdx)->getZExtValue()) { + default: + llvm_unreachable("Could not map int to register"); + case 0: return Mips::MSAIR; + case 1: return Mips::MSACSR; + case 2: return Mips::MSAAccess; + case 3: return Mips::MSASave; + case 4: return Mips::MSAModify; + case 5: return Mips::MSARequest; + case 6: return Mips::MSAMap; + case 7: return Mips::MSAUnmap; + } +} + bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr& MI) { unsigned DstReg = 0, ZeroReg = 0; @@ -432,6 +447,39 @@ std::pair MipsSEDAGToDAGISel::selectNode(SDNode *Node) { return std::make_pair(true, RegOpnd); } + case ISD::INTRINSIC_W_CHAIN: { + switch (cast(Node->getOperand(1))->getZExtValue()) { + default: + break; + + case Intrinsic::mips_cfcmsa: { + SDValue ChainIn = Node->getOperand(0); + SDValue RegIdx = Node->getOperand(2); + SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL, + getMSACtrlReg(RegIdx), MVT::i32); + return std::make_pair(true, Reg.getNode()); + } + } + break; + } + + case ISD::INTRINSIC_VOID: { + switch (cast(Node->getOperand(1))->getZExtValue()) { + default: + break; + + case Intrinsic::mips_ctcmsa: { + SDValue ChainIn = Node->getOperand(0); + SDValue RegIdx = Node->getOperand(2); + SDValue Value = Node->getOperand(3); + SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL, + getMSACtrlReg(RegIdx), Value); + return std::make_pair(true, ChainOut.getNode()); + } + } + break; + } + case MipsISD::ThreadPointer: { EVT PtrVT = getTargetLowering()->getPointerTy(); unsigned RdhwrOpc, DestReg; diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.h b/lib/Target/Mips/MipsSEISelDAGToDAG.h index 09a15b0..9961934 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.h +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.h @@ -30,6 +30,8 @@ private: void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, MachineFunction &MF); + unsigned getMSACtrlReg(const SDValue RegIdx) const; + bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&); std::pair selectMULT(SDNode *N, unsigned Opc, SDLoc dl, diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index e7967a8..374837e 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -110,6 +110,8 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); return; } + else if (Mips::MSACtrlRegClass.contains(SrcReg)) + Opc = Mips::CFCMSA; } else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. if (Mips::CCRRegClass.contains(DestReg)) @@ -130,6 +132,8 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addReg(DestReg, RegState::ImplicitDefine); return; } + else if (Mips::MSACtrlRegClass.contains(DestReg)) + Opc = Mips::CTCMSA; } else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) Opc = Mips::FMOV_S; -- cgit v1.1