From ab40f4b737b0a87c4048a9ad2f0c02be735e3770 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 20 Jul 2011 18:20:31 +0000 Subject: ARM assembly parsing of MUL instruction. Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'lib/Target') diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 0cf9a4a..89501dc 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1977,7 +1977,8 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic, // First, split out any predication code. Ignore mnemonics we know aren't // predicated but do have a carry-set and so weren't caught above. - if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") { + if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && + Mnemonic != "muls") { unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) -- cgit v1.1