From 113a06cff443f5d73c4f1f89bd31b0efb4222227 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Wed, 17 Nov 2010 00:55:36 +0000 Subject: Only avoid the check if we're the last operand before the variable operands in a variadic instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119446 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/MachineVerifier.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 47a94b3..f92b7fe 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -558,9 +558,9 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { else if (MO->isImplicit()) report("Explicit definition marked as implicit", MO, MONum); } else if (MONum < TI.getNumOperands()) { - // Don't check if it's a variadic instruction. See, e.g., LDM_RET in the arm - // back end. - if (MO->isReg() && MONum != TI.getNumOperands()-1) { + // Don't check if it's the last operand in a variadic instruction. See, + // e.g., LDM_RET in the arm back end. + if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) { if (MO->isDef()) report("Explicit operand marked as def", MO, MONum); if (MO->isImplicit()) -- cgit v1.1